On Wed, Sep 18, 2024 at 03:00:45AM +0000, Manikandan.M@xxxxxxxxxxxxx wrote: > On 17/09/24 6:08 pm, Conor Dooley wrote: > > On Tue, Sep 17, 2024 at 03:16:53AM +0000,Manikandan.M@xxxxxxxxxxxxx wrote: > >> Hi Conor, > >> > >> On 14/08/24 7:29 pm, Conor Dooley wrote: > >>> On Wed, Aug 14, 2024 at 04:22:53PM +0530, Manikandan Muralidharan wrote: > >>>> + microchip,sfr: > >>>> + $ref: /schemas/types.yaml#/definitions/phandle > >>>> + description: > >>>> + phandle to Special Function Register (SFR) node.To enable the DSI/CSI > >>>> + selection bit in SFR's ISS Configuration Register. > >>> I'm curious - why is this phandle required? How many SFR nodes are there > >>> on the platform? > >> This phandle is to map the memory region of SFR node and configure the > >> DSI bit in the SFR's ISS configuration register. > >> currently there is only one SFR node in this platform. > > What does "currently" mean? The platform either has one or it does not, > > currently makes it sound like it has more than one but the dts only has > > one. > Apologies, I would like to clarify the statement that this platform only > has one 32-bit special function register implemented. In that case, you dont need a phandle at all, just look the sfr up by its compatible.
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