Most ARM based chromebooks with two usb-c-connector nodes and one DP
controller are muxing the DP lanes between the two USB ports. This is
done so that the type-c ports are at least equal in capability if not
functionality. Either an analog mux is used to steer the DP signal to
one or the other port, or a DP bridge chip has two lanes (e.g. DP
ML0/ML1) wired to one type-c port while the other two (e.g. DP ML2/ML3)
are wired to another type-c port.
Implement the same algorithm that the EC has to figure out which type-c
port has actually been muxed for DP altmode. Wait for the first type-c
port to assert HPD, and treat that as the actively muxed port until the
port exits DP altmode entirely. Allow HPD to be asserted or deasserted
during this time. If the port isn't active, simply ignore those events
and skip calling cros_typec_enable_dp(). Otherwise, pass the DP
information to the typec subsystem so that the DP controller can respond
to HPD events and pin configurations.
The EC can mux the DP signal to any number of USB type-c ports. We only
need to make sure that the active USB type-c port is tracked so that DP
information about the other ports is ignored. Unfortunately, the EC
doesn't hide these details from the AP so we have to reimplement the
logic in the kernel.
Cc: Prashant Malani <pmalani@xxxxxxxxxxxx>
Cc: Benson Leung <bleung@xxxxxxxxxxxx>
Cc: Tzung-Bi Shih <tzungbi@xxxxxxxxxx>
Cc: <chrome-platform@xxxxxxxxxxxxxxx>
Cc: Pin-yen Lin <treapking@xxxxxxxxxxxx>
Signed-off-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
---
drivers/platform/chrome/cros_ec_typec.c | 31 +++++++++++++++++++++++--
drivers/platform/chrome/cros_ec_typec.h | 1 +
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
index a57053bdec18..57d1484ce1ef 100644
--- a/drivers/platform/chrome/cros_ec_typec.c
+++ b/drivers/platform/chrome/cros_ec_typec.c
@@ -639,6 +639,7 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num,
struct ec_response_usb_pd_control_v2 *pd_ctrl)
{
struct cros_typec_port *port = typec->ports[port_num];
+ bool has_dp_bridge = !!typec->dp_bridge;
struct ec_response_usb_pd_mux_info resp;
struct ec_params_usb_pd_mux_info req = {
.port = port_num,
@@ -646,6 +647,7 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num,
struct ec_params_usb_pd_mux_ack mux_ack;
enum typec_orientation orientation;
int ret;
+ bool dp_enabled, hpd_asserted, is_active_port;
ret = cros_ec_cmd(typec->ec, 0, EC_CMD_USB_PD_MUX_INFO,
&req, sizeof(req), &resp, sizeof(resp));
@@ -659,6 +661,25 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num,
if (port->mux_flags == resp.flags && port->role == pd_ctrl->role)
return 0;
+ dp_enabled = resp.flags & USB_PD_MUX_DP_ENABLED;
+ hpd_asserted = resp.flags & USB_PD_MUX_HPD_LVL;
+ /*
+ * Assume the first port to have HPD asserted is the one muxed to DP
+ * (i.e. active_port). When there's only one port this delays setting
+ * the active_port until HPD is asserted, but before that the
+ * drm_connector looks disconnected so active_port doesn't need to be
+ * set.
+ */
+ if (has_dp_bridge && hpd_asserted && !typec->active_dp_port)
+ typec->active_dp_port = port;
+
+ /*
+ * Skip calling cros_typec_enable_dp() for the non-active type-c port
+ * when muxing one DP to multiple type-c ports. This is only the case
+ * on platforms using a drm_bridge.
+ */
+ is_active_port = !has_dp_bridge || typec->active_dp_port == port;
+
port->mux_flags = resp.flags;
port->role = pd_ctrl->role;
@@ -686,8 +707,11 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num,
ret = cros_typec_enable_usb4(typec, port_num, pd_ctrl);
} else if (port->mux_flags & USB_PD_MUX_TBT_COMPAT_ENABLED) {
ret = cros_typec_enable_tbt(typec, port_num, pd_ctrl);
- } else if (port->mux_flags & USB_PD_MUX_DP_ENABLED) {
- ret = cros_typec_enable_dp(typec, port_num, pd_ctrl);
+ } else if (dp_enabled) {
+ ret = 0;
+ /* Ignore DP events for the non-active port */
+ if (is_active_port)
+ ret = cros_typec_enable_dp(typec, port_num, pd_ctrl);
} else if (port->mux_flags & USB_PD_MUX_SAFE_MODE) {
ret = cros_typec_usb_safe_state(port);
} else if (port->mux_flags & USB_PD_MUX_USB_ENABLED) {
@@ -704,6 +728,9 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num,
}
mux_ack:
+ if (has_dp_bridge && !dp_enabled && is_active_port)
+ typec->active_dp_port = NULL;
+
if (!typec->needs_mux_ack)
return ret;
diff --git a/drivers/platform/chrome/cros_ec_typec.h b/drivers/platform/chrome/cros_ec_typec.h
index eb816d30d880..f3a2b67df07c 100644
--- a/drivers/platform/chrome/cros_ec_typec.h
+++ b/drivers/platform/chrome/cros_ec_typec.h
@@ -36,6 +36,7 @@ struct cros_typec_data {
/* Array of ports, indexed by port number. */
struct cros_typec_port *ports[EC_USB_PD_MAX_PORTS];
struct drm_dp_typec_bridge_dev *dp_bridge;
+ struct cros_typec_port *active_dp_port;
struct notifier_block nb;
struct work_struct port_work;
bool typec_cmd_supported;
--
https://chromeos.dev
