On Sat, Aug 31, 2024 at 12:55:29AM +0300, Cristian Ciocaltea wrote: > Add dt-binding schema containing the common properties for the Synopsys > DesignWare HDMI QP TX controller. > > Note this is not a full dt-binding specification, but is meant to be > referenced by platform-specific bindings for this IP core. > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx> > --- > .../display/bridge/synopsys,dw-hdmi-qp.yaml | 88 ++++++++++++++++++++++ > 1 file changed, 88 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml > new file mode 100644 > index 000000000000..771f7fba6c50 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml > @@ -0,0 +1,88 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi-qp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Common Properties for Synopsys DesignWare HDMI QP TX Controller IP > + > +maintainers: > + - Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx> > + > +description: | > + The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX Controller IP core > + supports the following features, among others: > + > + * Fixed Rate Link (FRL) > + * Display Stream Compression (DSC) > + * 4K@120Hz and 8K@60Hz video modes > + * Variable Refresh Rate (VRR) including Quick Media Switching (QMS) > + * Fast Vactive (FVA) > + * SCDC I2C DDC access > + * Multi-stream audio > + * Enhanced Audio Return Channel (EARC) > + > + Note this is not a full dt-binding specification, but is meant to be > + referenced by platform-specific bindings for this IP core. > + > +properties: > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 4 > + maxItems: 6 > + items: > + - description: Peripheral/APB bus clock > + - description: EARC RX biphase clock > + - description: Reference clock > + - description: Audio interface clock > + additionalItems: true What is the usefulness of all this? How can you even be sure that each implementation of this core will have exactly these clocks? > + > + clock-names: > + minItems: 4 > + maxItems: 6 > + items: > + - const: pclk > + - const: earc > + - const: ref > + - const: aud > + additionalItems: true > + > + interrupts: > + minItems: 4 > + maxItems: 5 > + items: > + - description: AVP Unit interrupt > + - description: CEC interrupt > + - description: eARC RX interrupt > + - description: Main Unit interrupt If these are real pins, then this seems more possible, but additionalItems does not make me happy. I don't see much value in this schema and I am afraid even enforcing clock and interrupt names won't work for the second or third user. Best regards, Krzysztof
