Re: [PATCH v3] fix up the misspellings

Yang Ruibin <11162571@xxxxxxxx> · Mon, 26 Aug 2024 12:15:30 +0800

Sorry, please ignore this patch for now.  As the wrong subject line.  
This patch will be updated later.

在 2024/8/26 10:55, Yang Ruibin 写道:
Hightest is a typo. It should be highest.Please ensure
the consistency of variable naming.

Signed-off-by: Yang Ruibin <11162571@xxxxxxxx>
---
Changes V3:
-Updated the ignored misspellings
---
  .../drm/amd/pm/powerplay/smumgr/fiji_smumgr.c    | 16 ++++++++--------
  .../amd/pm/powerplay/smumgr/polaris10_smumgr.c   | 16 ++++++++--------
  .../drm/amd/pm/powerplay/smumgr/vegam_smumgr.c   | 16 ++++++++--------
  3 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
index 5e43ad2b2956..e16efc44df88 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
@@ -1014,7 +1014,7 @@ static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
  	struct SMU73_Discrete_GraphicsLevel *levels =
  			smu_data->smc_state_table.GraphicsLevel;
  	uint32_t i, max_entry;
-	uint8_t hightest_pcie_level_enabled = 0,
+	uint8_t highest_pcie_level_enabled = 0,
  			lowest_pcie_level_enabled = 0,
  			mid_pcie_level_enabled = 0,
  			count = 0;
@@ -1054,27 +1054,27 @@ static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
  	} else {
  		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
  				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-						(1 << (hightest_pcie_level_enabled + 1))) != 0))
-			hightest_pcie_level_enabled++;
+						(1 << (highest_pcie_level_enabled + 1))) != 0))
+			highest_pcie_level_enabled++;
  
  		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
  				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
  						(1 << lowest_pcie_level_enabled)) == 0))
  			lowest_pcie_level_enabled++;
  
-		while ((count < hightest_pcie_level_enabled) &&
+		while ((count < highest_pcie_level_enabled) &&
  				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
  						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
  			count++;
  
  		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
-				hightest_pcie_level_enabled ?
+				highest_pcie_level_enabled ?
  						(lowest_pcie_level_enabled + 1 + count) :
-						hightest_pcie_level_enabled;
+						highest_pcie_level_enabled;
  
-		/* set pcieDpmLevel to hightest_pcie_level_enabled */
+		/* set pcieDpmLevel to highest_pcie_level_enabled */
  		for (i = 2; i < dpm_table->sclk_table.count; i++)
-			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
+			levels[i].pcieDpmLevel = highest_pcie_level_enabled;
  
  		/* set pcieDpmLevel to lowest_pcie_level_enabled */
  		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
index ff6b563ecbf5..d785cc6468ef 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
@@ -1050,7 +1050,7 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
  	struct SMU74_Discrete_GraphicsLevel *levels =
  			smu_data->smc_state_table.GraphicsLevel;
  	uint32_t i, max_entry;
-	uint8_t hightest_pcie_level_enabled = 0,
+	uint8_t highest_pcie_level_enabled = 0,
  		lowest_pcie_level_enabled = 0,
  		mid_pcie_level_enabled = 0,
  		count = 0;
@@ -1114,27 +1114,27 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
  	} else {
  		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
  				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-						(1 << (hightest_pcie_level_enabled + 1))) != 0))
-			hightest_pcie_level_enabled++;
+						(1 << (highest_pcie_level_enabled + 1))) != 0))
+			highest_pcie_level_enabled++;
  
  		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
  				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
  						(1 << lowest_pcie_level_enabled)) == 0))
  			lowest_pcie_level_enabled++;
  
-		while ((count < hightest_pcie_level_enabled) &&
+		while ((count < highest_pcie_level_enabled) &&
  				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
  						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
  			count++;
  
  		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
-				hightest_pcie_level_enabled ?
+				highest_pcie_level_enabled ?
  						(lowest_pcie_level_enabled + 1 + count) :
-						hightest_pcie_level_enabled;
+						highest_pcie_level_enabled;
  
-		/* set pcieDpmLevel to hightest_pcie_level_enabled */
+		/* set pcieDpmLevel to highest_pcie_level_enabled */
  		for (i = 2; i < dpm_table->sclk_table.count; i++)
-			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
+			levels[i].pcieDpmLevel = highest_pcie_level_enabled;
  
  		/* set pcieDpmLevel to lowest_pcie_level_enabled */
  		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
index 34c9f59b889a..3e73f380a591 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
@@ -878,7 +878,7 @@ static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
  	struct SMU75_Discrete_GraphicsLevel *levels =
  			smu_data->smc_state_table.GraphicsLevel;
  	uint32_t i, max_entry;
-	uint8_t hightest_pcie_level_enabled = 0,
+	uint8_t highest_pcie_level_enabled = 0,
  		lowest_pcie_level_enabled = 0,
  		mid_pcie_level_enabled = 0,
  		count = 0;
@@ -925,27 +925,27 @@ static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
  	} else {
  		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
  				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-						(1 << (hightest_pcie_level_enabled + 1))) != 0))
-			hightest_pcie_level_enabled++;
+						(1 << (highest_pcie_level_enabled + 1))) != 0))
+			highest_pcie_level_enabled++;
  
  		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
  				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
  						(1 << lowest_pcie_level_enabled)) == 0))
  			lowest_pcie_level_enabled++;
  
-		while ((count < hightest_pcie_level_enabled) &&
+		while ((count < highest_pcie_level_enabled) &&
  				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
  						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
  			count++;
  
  		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
-				hightest_pcie_level_enabled ?
+				highest_pcie_level_enabled ?
  						(lowest_pcie_level_enabled + 1 + count) :
-						hightest_pcie_level_enabled;
+						highest_pcie_level_enabled;
  
-		/* set pcieDpmLevel to hightest_pcie_level_enabled */
+		/* set pcieDpmLevel to highest_pcie_level_enabled */
  		for (i = 2; i < dpm_table->sclk_table.count; i++)
-			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
+			levels[i].pcieDpmLevel = highest_pcie_level_enabled;
  
  		/* set pcieDpmLevel to lowest_pcie_level_enabled */
  		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;






