On 22/08/24 9:36 PM, Nícolas F. R. A. Prado wrote:
On Thu, Aug 22, 2024 at 06:46:50AM +0000, Rohit Agarwal wrote:
Add clock/irq/efuse setting in svs nodes for mt8186 SoC.
Signed-off-by: Rohit Agarwal <rohiagar@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index e27c69ec8bdd..a51f3d8ce745 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1361,6 +1361,18 @@ spi0: spi@1100a000 {
status = "disabled";
};
+ svs: svs@1100b000 {
There's already another node at address 1100b000:
lvts: thermal-sensor@1100b000
You should set the starting address of the SVS to 1100bc00 and decrease the
iospace for lvts to avoid intersection. See this commit for a similar change on
mt8195:
https://lore.kernel.org/all/20231121125044.78642-21-angelogioacchino.delregno@xxxxxxxxxxxxx/
Sure. Will update this according to the reference.
Thanks,
Rohit.
