In commit ea315f98e5d6 ("drm/i915/gt: Do not generate the command
streamer for all the CCS"), we restricted the creation of
physical CCS engines to only one stream. This allowed the user to
submit a single compute workload, with all CCS slices sharing the
workload from that stream.
This patch removes that limitation but still exposes only one
stream to the user. The physical memory for each engine remains
allocated but unused, however the user will only see one engine
exposed.
Do this by adding only one engine to the UABI list, ensuring that
only one engine is visible to the user.
Signed-off-by: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 23 ---------------------
drivers/gpu/drm/i915/gt/intel_engine_user.c | 20 +++++++++++++++---
2 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 4d30a86016f2..def255ee0b96 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -876,29 +876,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
info->engine_mask &= ~BIT(GSC0);
}
- /*
- * Do not create the command streamer for CCS slices beyond the first.
- * All the workload submitted to the first engine will be shared among
- * all the slices.
- *
- * Once the user will be allowed to customize the CCS mode, then this
- * check needs to be removed.
- */
- if (IS_DG2(gt->i915)) {
- u8 first_ccs = __ffs(CCS_MASK(gt));
-
- /*
- * Store the number of active cslices before
- * changing the CCS engine configuration
- */
- gt->ccs.cslices = CCS_MASK(gt);
-
- /* Mask off all the CCS engine */
- info->engine_mask &= ~GENMASK(CCS3, CCS0);
- /* Put back in the first CCS engine */
- info->engine_mask |= BIT(_CCS(first_ccs));
- }
-
return info->engine_mask;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 11cc06c0c785..c5ccb677ed15 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -207,6 +207,7 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
struct legacy_ring ring = {};
struct list_head *it, *next;
struct rb_node **p, *prev;
+ u8 uabi_ccs_instance = 0;
LIST_HEAD(engines);
sort_engines(i915, &engines);
@@ -246,6 +247,22 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
GEM_BUG_ON(uabi_class >=
ARRAY_SIZE(i915->engine_uabi_class_count));
+
+ /* Fix up the mapping to match default execbuf::user_map[] */
+ add_legacy_ring(&ring, engine);
+
+ /*
+ * Do not create the command streamer for CCS slices beyond the
+ * first. All the workload submitted to the first engine will be
+ * shared among all the slices.
+ */
+ if (IS_DG2(i915) && uabi_class == I915_ENGINE_CLASS_COMPUTE) {
+ uabi_ccs_instance++;
+
+ if (uabi_ccs_instance > 1)
+ continue;
+ }
+
i915->engine_uabi_class_count[uabi_class]++;
rb_link_node(&engine->uabi_node, prev, p);
@@ -255,9 +272,6 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
engine->uabi_class,
engine->uabi_instance) != engine);
- /* Fix up the mapping to match default execbuf::user_map[] */
- add_legacy_ring(&ring, engine);
-
prev = &engine->uabi_node;
p = &prev->rb_right;
}
--
2.45.2
