Applied. Thanks! On Wed, Jul 31, 2024 at 3:20 AM Remington Brasga <rbrasga@xxxxxxx> wrote: > > A few define's are listed twice with different, incorrect values. > This fix sets them appropriately. > > Signed-off-by: Remington Brasga <rbrasga@xxxxxxx> > --- > The second UVD_LMI_CTRL__RFU_MASK is incorrect, so it was removed. It should be > `0xf800 0000`. > The first UVD_LMI_CTRL__RFU__SHIFT is incorrect, so it was removed. > It should bei `0x1a`. > > This change aligns the uvd definitions, please refer to: > drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h > drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h > drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h > drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h > > drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h > index 8ee3149df5b7..2ef1273e65ab 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h > @@ -340,8 +340,6 @@ > #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L > #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x00000009 > #define UVD_LMI_CTRL__RFU_MASK 0xf8000000L > -#define UVD_LMI_CTRL__RFU_MASK 0xfc000000L > -#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001a > #define UVD_LMI_CTRL__RFU__SHIFT 0x0000001b > #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L > #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015 > -- > 2.34.1 >
