Hi Biju,
Thank you for the patch.
On Tue, Jul 09, 2024 at 02:51:45PM +0100, Biju Das wrote:
> Add fcpvd node to RZ/G2UL SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx>
> ---
> v1->v2:
> * No change.
> ---
> arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> index 15e84a5428ef..d88bf23b0782 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> @@ -142,6 +142,17 @@ vspd: vsp@10870000 {
> renesas,fcp = <&fcpvd>;
> };
>
> + fcpvd: fcp@10880000 {
> + compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv";
> + reg = <0 0x10880000 0 0x10000>;
> + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
> + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
> + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
> + clock-names = "aclk", "pclk", "vclk";
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_LCDC_RESET_N>;
> + };
> +
> irqc: interrupt-controller@110a0000 {
> compatible = "renesas,r9a07g043u-irqc",
> "renesas,rzg2l-irqc";
--
Regards,
Laurent Pinchart
