> > A later change will use the FE debug registers to improve GPU > progress monitoring. Instead of having to keep track of the > usage state of the debug registers and lock access to the > VIVS_HI_CLOCK_CONTROL register, statically enable debug > register access during GPU init. > > The Vivante downstream driver seems to do the same thing since > a while, so it should be okay to keep access enabled. (See > gckHARDWARE_InitializeHardware in 6.4.11 downstream driver). > > Many debug registers contain bogus data if clock gating is > enabled, so even if they are always accessible performance > profiling still needs to manage some prerequisites. > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> Reviewed-by: Christian Gmeiner <cgmeiner@xxxxxxxxxx> > --- > v2: new patch replacing more complex usage tracking from v1 > --- > drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 14 ++------------ > 1 file changed, 2 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c > index 2bd14d3501e2..bf0b13c99a3c 100644 > --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c > +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c > @@ -574,8 +574,8 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) > continue; > } > > - /* disable debug registers, as they are not normally needed */ > - control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; > + /* enable debug register access */ > + control &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; > gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); > > failed = false; > @@ -1337,11 +1337,6 @@ static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, > val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; > gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); > > - /* enable debug register */ > - val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); > - val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; > - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); > - > sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); > > mutex_unlock(&gpu->lock); > @@ -1358,11 +1353,6 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, > > sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); > > - /* disable debug register */ > - val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); > - val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; > - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); > - > /* enable clock gating */ > val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); > val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; > -- > 2.39.2 > -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info/privacypolicy
