On Tue, 25 Jun 2024 14:02:30 +0200, Marek Vasut wrote:
> Split tc_pxl_pll_en() into tc_pxl_pll_calc() which does only Pixel PLL
> parameter calculation and tc_pxl_pll_en() which calls tc_pxl_pll_calc()
> and then configures the Pixel PLL register.
>
> This is a preparatory patch for further rework, where tc_pxl_pll_calc()
> will also be used to find out the exact clock frequency generated by the
> Pixel PLL. This frequency will be used as adjusted_mode clock frequency
> and passed down the display pipeline to obtain exactly this frequency
> on input into this bridge.
>
> [...]
Applied, thanks!
[1/5] drm/bridge: tc358767: Split tc_pxl_pll_en() into parameter calculation and enablement
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=84708c2d180c
[2/5] drm/bridge: tc358767: Use tc_pxl_pll_calc() to correct adjusted_mode clock
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=a723d434009e
[3/5] drm/bridge: tc358767: Drop line_pixel_subtract
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=3f13e53bcf30
[4/5] drm/bridge: tc358767: Set LSCLK divider for SYSCLK to 1
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=9c433c87e81c
[5/5] Revert "drm/bridge: tc358767: Set default CLRSIPO count"
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=86b0e0c1ad47
Rob
