https://bugzilla.kernel.org/show_bug.cgi?id=60858 --- Comment #9 from Pinak Ahuja <pinak.ahuja@xxxxxxxxx> --- (In reply to Christian König from comment #8) > You could dig into the code and try to figure out why the post dividers > (vclk_div and dclk_div) turn out as 0. > > The two involved functions are rv770_set_uvd_clocks which can be found here > drivers/gpu/drm/radeon/rv770.c and radeon_uvd_calc_upll_dividers which can > be found here drivers/gpu/drm/radeon/radeon_uvd.c. I'll go through the code a little later and see if i can find something useful. > The most interesting value is rdev->clock.spll.reference_freq, it is the > reference clock frequency coming from a bios table. If that is wrong the > whole calculation doesn't work any more and the UPLL generates an invalid > frequency. > > Insert something like DRM_ERROR("Test %d\n", > rdev->clock.spll.reference_freq) into the code and see what it spits out on > the next reboot. I did this, heres the output: [ 8.346601] [drm:radeon_uvd_calc_upll_dividers] *ERROR* Test 2700 here's the full log: http://pastebin.com/31Pe119f -- You are receiving this mail because: You are watching the assignee of the bug. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
