https://bugzilla.kernel.org/show_bug.cgi?id=60858 --- Comment #8 from Christian König <christian.koenig@xxxxxxx> --- You could dig into the code and try to figure out why the post dividers (vclk_div and dclk_div) turn out as 0. The two involved functions are rv770_set_uvd_clocks which can be found here drivers/gpu/drm/radeon/rv770.c and radeon_uvd_calc_upll_dividers which can be found here drivers/gpu/drm/radeon/radeon_uvd.c. The most interesting value is rdev->clock.spll.reference_freq, it is the reference clock frequency coming from a bios table. If that is wrong the whole calculation doesn't work any more and the UPLL generates an invalid frequency. Insert something like DRM_ERROR("Test %d\n", rdev->clock.spll.reference_freq) into the code and see what it spits out on the next reboot. Unfortunately I currently don't have much time to look into this and it seems to still work fine with my RV710, so it must be something special with your laptop. -- You are receiving this mail because: You are watching the assignee of the bug. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
