On Mon, 13 May 2024 04:16:04 +0200, Marek Vasut wrote:
> TC9595 datasheet Video Path0 Control (VPCTRL0) Register bit FRMSYNC description
> says "This bit should be disabled only in video mode transmission where Host
> transmits video timing together with video data and where pixel clock source
> is from DSI clock." . This driver always sources pixel clock from external xtal,
> therefore the FRMSYNC bit must always be enabled, enable it.
>
> This fixes an actual issue with DSI-to-DPI mode, where the display would
> randomly show subtle pixel flickering, or wobble, or shimmering. This is
> visible on solid gray color, but the degree of the shimmering differs
> between boots, which makes it hard to debug.
>
> [...]
Applied, thanks!
[1/1] drm/bridge: tc358767: Enable FRMSYNC timing generator
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=d9ca4b760ef6
Rob
