On Fri, Apr 26, 2024 at 02:07:23AM +0200, Andi Shyti wrote: > We missed setting the CCS mode during resume and engine resets. > Create a workaround to be added in the engine's workaround list. > This workaround sets the XEHP_CCS_MODE value at every reset. > > The issue can be reproduced by running: > > $ clpeak --kernel-latency > > Without resetting the CCS mode, we encounter a fence timeout: > > Fence expiration time out i915-0000:03:00.0:clpeak[2387]:2! > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895 > Fixes: 6db31251bb26 ("drm/i915/gt: Enable only one CCS for compute workload") > Reported-by: Gnattu OC <gnattuoc@xxxxxx> > Signed-off-by: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx> > Cc: Chris Wilson <chris.p.wilson@xxxxxxxxxxxxxxx> > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > Cc: Matt Roper <matthew.d.roper@xxxxxxxxx> > Cc: <stable@xxxxxxxxxxxxxxx> # v6.2+ Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > Hi Gnattu, > > thanks again for reporting this issue and for your prompt > replies on the issue. Would you give this patch a chance? > > Andi > > drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 6 +++--- > drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 +++- > 3 files changed, 7 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c > index 044219c5960a..99b71bb7da0a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c > @@ -8,14 +8,14 @@ > #include "intel_gt_ccs_mode.h" > #include "intel_gt_regs.h" > > -void intel_gt_apply_ccs_mode(struct intel_gt *gt) > +unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) > { > int cslice; > u32 mode = 0; > int first_ccs = __ffs(CCS_MASK(gt)); > > if (!IS_DG2(gt->i915)) > - return; > + return 0; > > /* Build the value for the fixed CCS load balancing */ > for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { > @@ -35,5 +35,5 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt) > XEHP_CCS_MODE_CSLICE_MASK); > } > > - intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode); > + return mode; > } > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h > index 9e5549caeb26..55547f2ff426 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h > @@ -8,6 +8,6 @@ > > struct intel_gt; > > -void intel_gt_apply_ccs_mode(struct intel_gt *gt); > +unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); > > #endif /* __INTEL_GT_CCS_MODE_H__ */ > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 68b6aa11bcf7..58693923bf6c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2703,6 +2703,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt, > static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) > { > struct intel_gt *gt = engine->gt; > + u32 mode; > > if (!IS_DG2(gt->i915)) > return; > @@ -2719,7 +2720,8 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li > * After having disabled automatic load balancing we need to > * assign all slices to a single CCS. We will call it CCS mode 1 > */ > - intel_gt_apply_ccs_mode(gt); > + mode = intel_gt_apply_ccs_mode(gt); > + wa_masked_en(wal, XEHP_CCS_MODE, mode); > } > > /* > -- > 2.43.0 >
