Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 





On 4/11/24 23:46, Dmitry Baryshkov wrote:
On Fri, 12 Apr 2024 at 00:35, Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> wrote:



On 4/10/24 21:26, Dmitry Baryshkov wrote:
On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote:


On 4/6/24 05:23, Dmitry Baryshkov wrote:
On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
abstracted through SMEM, instead of being directly available in a fuse.

Add support for SMEM-based speed binning, which includes getting
"feature code" and "product code" from said source and parsing them
to form something that lets us match OPPs against.

Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
---

[...]


+  }
+
+  ret = qcom_smem_get_product_code(&pcode);
+  if (ret) {
+          dev_err(dev, "Couldn't get product code from SMEM!\n");
+          return ret;
+  }
+
+  /* Don't consider fcode for external feature codes */
+  if (fcode <= SOCINFO_FC_EXT_RESERVE)
+          fcode = SOCINFO_FC_UNKNOWN;
+
+  *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) |
+              FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode);

What about just asking the qcom_smem for the 'gpu_bin' and hiding gory
details there? It almost feels that handling raw PCODE / FCODE here is
too low-level and a subject to change depending on the socinfo format.

No, the FCODE & PCODE can be interpreted differently across consumers.

That's why I wrote about asking for 'gpu_bin'.

I'd rather keep the magic GPU LUTs inside the adreno driver, especially
since not all Snapdragons feature Adreno, but all Adrenos are on
Snapdragons (modulo a2xx but I refuse to make design decisions treating
these equally to e.g. a6xx)

LUTs - yes. I wanted to push (FC << a) | (PC << b) and all the RESERVE
/ UNKNOWN magic there.

Ohh this specifically.. yeah I considered pushing that there as well,
but I realized this is specific to the GPU. The socinfo APIs should
only return a valid/unknown code for both P and F and let the consumer
figure out how to interpret these.






+
+  return ret;
    }
    int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
@@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                            devm_pm_opp_set_clkname(dev, "core");
            }
-  if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
+  if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin)
                    speedbin = 0xffff;
-  adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);

the &= 0xffff should probably go to the adreno_read_speedbin / nvmem
case. WDYT?

Ok, I can keep it, though realistically if this ever does anything
useful, it likely means the dt is wrong

Yes, but if DT is wrong, we should probably fail in a sensible way. I
just wanted to point out that previously we had this &0xffff, while your
patch silently removes it.

Right, but I don't believe it actually matters.. If that AND ever did
anything, this was a silent failure with garbage data passed in anyway.

If you really insist, I can remove it separately.

I'd say, up to Rob or up to your consideration.

Konrad



[Index of Archives]     [Linux DRI Users]     [Linux Intel Graphics]     [Linux USB Devel]     [Video for Linux]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]     [XFree86]     [Linux USB Devel]     [Video for Linux]     [Linux Audio Users]     [Linux Kernel]     [Linux SCSI]     [XFree86]
  Powered by Linux