On Mon, Apr 8, 2024 at 6:16 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> wrote: > > Il 08/04/24 05:20, Chen-Yu Tsai ha scritto: > > On Thu, Apr 4, 2024 at 4:16 PM AngeloGioacchino Del Regno > > <angelogioacchino.delregno@xxxxxxxxxxxxx> wrote: > >> > >> Document OF graph on MMSYS/VDOSYS: this supports up to three DDP paths > >> per HW instance (so potentially up to six displays for multi-vdo SoCs). > >> > >> The MMSYS or VDOSYS is always the first component in the DDP pipeline, > >> so it only supports an output port with multiple endpoints - where each > >> endpoint defines the starting point for one of the (currently three) > >> possible hardware paths. > >> > >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> > >> --- > >> .../bindings/arm/mediatek/mediatek,mmsys.yaml | 23 +++++++++++++++++++ > >> 1 file changed, 23 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > >> index b3c6888c1457..90758bb5bcb1 100644 > >> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > >> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > >> @@ -93,6 +93,29 @@ properties: > >> '#reset-cells': > >> const: 1 > >> > >> + port: > >> + $ref: /schemas/graph.yaml#/properties/port > >> + description: > >> + Output port node. This port connects the MMSYS/VDOSYS output to > >> + the first component of one display pipeline, for example one of > >> + the available OVL or RDMA blocks. > >> + Some MediaTek SoCs support up to three display outputs per MMSYS. > >> + properties: > >> + endpoint@0: > >> + $ref: /schemas/graph.yaml#/properties/endpoint > >> + description: Output to the primary display pipeline > >> + > >> + endpoint@1: > >> + $ref: /schemas/graph.yaml#/properties/endpoint > >> + description: Output to the secondary display pipeline > >> + > >> + endpoint@2: > >> + $ref: /schemas/graph.yaml#/properties/endpoint > >> + description: Output to the tertiary display pipeline > >> + > >> + required: > >> + - endpoint@0 > >> + > > > > Technically the mmsys device serves as an glue layer for the display > > pipeline, providing things like clock control and signal routing; the > > device itself is not part of the pipeline, and probably shouldn't be > > part of the graph? > > > > That is (only) partially true: in the case of older SoCs, the MMSYS can only > connect to a single first IP of the pipeline, but in the case of newer ones, > and especially (but not limited to) MT8195 onwards having multiple instances > of VDOSYS, that really becomes part of the pipeline. > > This is not because of the possible different first IP in the pipeline, but > because of support for dual-interface (DSI and DP) that, in even newer SoCs, > can be done with cross-mmsys (cross-vdosys, actually...) as some of those do > have the two in different VDOs. > > So yes, this can be done without the graph in MMSYS *in this precise moment in > time*, but we'll anyway end up adding it sooner than later - and I'm doing this > right now, instead of later, because it's also simplifying the implementation > so like that I'm "catching two birds with one stone" :-) I see. Thanks for sorting it out. We had something similar on Allwinner platforms but it was never as complex or flexible as this. ChenYu > Cheers, > Angelo > > > ChenYu > > > >> required: > >> - compatible > >> - reg > >> -- > >> 2.44.0 > >> > >
