Hi Sean, On Fri, Mar 08, 2024 at 09:35:27AM +0100, Sean Nyekjaer wrote: > I’m using a stm32mp157 with a sn65dsi83 DSI2LVDS bridge. The LVDS > display is having a minimum clock of 25.2 MHz, typical of 27,2 MHz and > a max of 30,5 MHz. > > I will fail the mode_valid check with MODE_CLOCK_RANGE. It will > request 27200000 Hz, but is getting 27250000. Guess the display is > fine with this :) > > In this case it seems a bit harsh to fail if the output clock isn’t > within 50 Hz of the requested clock. Even for HDMI, the tolerance is usually .5% of the pixel clock. 50Hz seems overly restrictive. > If HDMI is requiring a tolerance of 50 Hz, would it be better to do > the check in the HDMI bridge driver? Judging from the code, it would be hard to do because the clock that generates the pixel clock isn't exposed to the HDMI bridge. Maxime
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