2013/8/14 Alex Deucher <alexdeucher@xxxxxxxxx>:
> Similar to DCE4/5, but supports multiple audio pins
> which can be assigned per afmt block.
Acked-by: Rafał Miłecki <zajec5@xxxxxxxxx>
Tested successfully on my HD7750.
> +static void r600_audio_enable(struct radeon_device *rdev,
> + struct r600_audio_pin *pin,
> + bool enable)
> {
> u32 value = 0;
> - DRM_INFO("%s audio support\n", enable ? "Enabling" : "Disabling");
Whoops, that confused me at the beginning. Don't you think it's nice
to know from somebody's dmesg if he uses radeon.audio or now? For
debugging purposes.
> +#define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
> +#define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
> +#define SPEAKER_ALLOCATION_MASK (0x7f << 0)
> +#define SPEAKER_ALLOCATION_SHIFT 0
> +#define HDMI_CONNECTION (1 << 16)
> +#define DP_CONNECTION (1 << 17)
Could you share a meaning of 0x00c00000 bit? I noticed it's set when
fglrx reads this register:
WREG32(0x00005e00, 0x00000025);
RREG32(0x00005e04); -> 0x00c00000
WREG32(0x00005e00, 0x00000125);
WREG32(0x00005e04, 0x00c1005f);
but it's not set with radeon reads it for the first time. Maybe fglrx
sets that at some other stage (earlier)?
--
Rafał
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