Hi Sato-san, On Tue, Jan 9, 2024 at 9:24 AM Yoshinori Sato <ysato@xxxxxxxxxxxxxxxxxxxx> wrote: > divider and gate only support 32-bit registers. > Older hardware uses narrower registers, so I want to be able to handle > 8-bit and 16-bit wide registers. > > Seven clk_divider flags are used, and if I add flags for 8bit access and > 16bit access, 8bit will not be enough, so I expanded it to u16. > > Signed-off-by: Yoshinori Sato <ysato@xxxxxxxxxxxxxxxxxxxx> Thanks for your patch! > --- a/drivers/clk/clk-gate.c > +++ b/drivers/clk/clk-gate.c > @@ -143,6 +161,18 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev, > return ERR_PTR(-EINVAL); > } Please add a check for invalid CLK_GATE_HIWORD_MASK and register width combinations: if (clk_gate_flags & (CLK_GATE_REG_16BIT | CLK_GATE_REG_8BIT)) { pr_err("HIWORD_MASK needs 32-bit registers\n"); return ERR_PTR(-EINVAL); } > } > + if (clk_gate_flags & CLK_GATE_REG_16BIT) { > + if (bit_idx > 15) { > + pr_err("gate bit exceeds 16 bits\n"); > + return ERR_PTR(-EINVAL); > + } > + } > + if (clk_gate_flags & CLK_GATE_REG_8BIT) { > + if (bit_idx > 7) { > + pr_err("gate bit exceeds 8 bits\n"); > + return ERR_PTR(-EINVAL); > + } > + } > > /* allocate the gate */ > gate = kzalloc(sizeof(*gate), GFP_KERNEL); > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h > index ace3a4ce2fc9..e2dfc1f083f4 100644 > --- a/include/linux/clk-provider.h > +++ b/include/linux/clk-provider.h > @@ -508,12 +508,16 @@ void of_fixed_clk_setup(struct device_node *np); > * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for > * the gate register. Setting this flag makes the register accesses big > * endian. > + * CLK_GATE_REG_8BIT - by default 32bit register accesses are used for > + * the gate register. Setting this flag makes the register accesses 8bit. > + * CLK_GATE_REG_16BIT - by default 32bit register accesses are used for > + * the gate register. Setting this flag makes the register accesses 16bit. > */ > struct clk_gate { > struct clk_hw hw; > void __iomem *reg; > u8 bit_idx; > - u8 flags; > + u32 flags; There is no need to increase the size of the flags field for the gate clock. > spinlock_t *lock; > }; > > @@ -522,6 +526,8 @@ struct clk_gate { > #define CLK_GATE_SET_TO_DISABLE BIT(0) > #define CLK_GATE_HIWORD_MASK BIT(1) > #define CLK_GATE_BIG_ENDIAN BIT(2) > +#define CLK_GATE_REG_8BIT BIT(3) > +#define CLK_GATE_REG_16BIT BIT(4) > > extern const struct clk_ops clk_gate_ops; > struct clk_hw *__clk_hw_register_gate(struct device *dev, The rest LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds