Re: [PATCH 3/6] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP

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On 2/22/2024 5:42 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.

--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]

--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@xxxxxxxxx>
---
  .../drm/i915/display/intel_display_types.h    |  1 +
  drivers/gpu/drm/i915/display/intel_dp.c       | 89 ++++++++++++++++++-
  drivers/gpu/drm/i915/display/intel_hdmi.c     | 12 ++-
  drivers/gpu/drm/i915/display/intel_vrr.c      |  5 ++
  drivers/gpu/drm/i915/i915_reg.h               |  8 ++
  5 files changed, 111 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a6991bc3f07b..2accfe41160d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1414,6 +1414,7 @@ struct intel_crtc_state {
  		bool enable, in_range;
  		u8 pipeline_full;
  		u16 flipline, vmin, vmax, guardband;
+		u8 as_sdp_mode;


I think this is DP specific, lets not add this thing here.


  	} vrr;
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 217196196e50..b370e1da4735 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -95,7 +95,6 @@
  #define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  #define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
-
  /* Constants for DP DSC configurations */
  static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
@@ -4089,6 +4088,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
  	return false;
  }
+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
+				    struct dp_sdp *sdp, size_t size)
+{
+	size_t length = sizeof(struct dp_sdp);
+
+	if (size < length)
+		return -ENOSPC;
+
+	memset(sdp, 0, size);
+
+	/* Prepare AS (Adaptive Sync) SDP Header */
+	sdp->sdp_header.HB0 = 0;
+	sdp->sdp_header.HB1 = as_sdp->sdp_type;
+	sdp->sdp_header.HB2 = 0x02;
+	sdp->sdp_header.HB3 = as_sdp->length;
+
+	/* Fill AS (Adaptive Sync) SDP Payload */
+	sdp->db[0] = as_sdp->mode;
+	sdp->db[1] = as_sdp->vtotal & 0xFF;
+	sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
+	sdp->db[3] = as_sdp->target_rr;
+	sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
+
+	return length;
+}
+
  static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
  				     struct dp_sdp *sdp, size_t size)
  {
@@ -4256,6 +4281,10 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
  							       &crtc_state->infoframes.drm.drm,
  							       &sdp, sizeof(sdp));
  		break;
+	case DP_SDP_ADAPTIVE_SYNC:
+		len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
+					   sizeof(sdp));
+		break;
  	default:
  		MISSING_CASE(type);
  		return;
@@ -4276,7 +4305,8 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
  	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
  	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
  			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
-			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
+			 VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
  	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
@@ -4298,6 +4328,36 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
  	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
  }
+static
+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
+			   const void *buffer, size_t size)
+{
+	const struct dp_sdp *sdp = buffer;
+
+	if (size < sizeof(struct dp_sdp))
+		return -EINVAL;
+
+	memset(as_sdp, 0, sizeof(*as_sdp));
+
+	if (sdp->sdp_header.HB0 != 0)
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
+		return -EINVAL;
+
+	if (sdp->sdp_header.HB2 != 0x02)
+		return -EINVAL;
+
+	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
+		return -EINVAL;
+
+	as_sdp->mode = sdp->db[0] & AS_SDP_OP_MODE;
+	as_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1];
+	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+
+	return 0;
+}
+
  static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
  				   const void *buffer, size_t size)
  {
@@ -4368,6 +4428,27 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
  	return 0;
  }
+static int
+intel_read_dp_metadata_infoframe_as_sdp(struct intel_encoder *encoder,


Drop metadata here.


+					struct intel_crtc_state *crtc_state,
+					struct drm_dp_as_sdp *as_sdp)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	unsigned int type = DP_SDP_ADAPTIVE_SYNC;
+	struct dp_sdp sdp = {};
+	int ret;
+
+	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
+				 sizeof(sdp));
+
+	ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
+	if (ret)
+		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");
+
+	return ret;
+}
+
  static int
  intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
  					   const void *buffer, size_t size)
@@ -4474,6 +4555,10 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
  		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
  							 &crtc_state->infoframes.drm.drm);
  		break;
+	case DP_SDP_ADAPTIVE_SYNC:
+		intel_read_dp_metadata_infoframe_as_sdp(encoder, crtc_state,
+							&crtc_state->infoframes.as_sdp);
+		break;
  	default:
  		MISSING_CASE(type);
  		break;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7020e5806109..69e0876f43aa 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -137,6 +137,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
  		return VIDEO_DIP_ENABLE_GMP_HSW;
  	case DP_SDP_VSC:
  		return VIDEO_DIP_ENABLE_VSC_HSW;
+	case DP_SDP_ADAPTIVE_SYNC:
+		return VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
  	case DP_SDP_PPS:
  		return VDIP_ENABLE_PPS;
  	case HDMI_INFOFRAME_TYPE_AVI:
@@ -164,6 +166,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
  		return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
  	case DP_SDP_VSC:
  		return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+	case DP_SDP_ADAPTIVE_SYNC:
+		return TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i);
  	case DP_SDP_PPS:
  		return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
  	case HDMI_INFOFRAME_TYPE_AVI:
@@ -186,6 +190,8 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
  	switch (type) {
  	case DP_SDP_VSC:
  		return VIDEO_DIP_VSC_DATA_SIZE;
+	case DP_SDP_ADAPTIVE_SYNC:
+		return VIDEO_DIP_ASYNC_DATA_SIZE;
  	case DP_SDP_PPS:
  		return VIDEO_DIP_PPS_DATA_SIZE;
  	case HDMI_PACKET_TYPE_GAMUT_METADATA:
@@ -558,7 +564,8 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
  		VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-		VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+		VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+		VIDEO_DIP_ENABLE_ADAPTIVE_SYNC);
if (DISPLAY_VER(dev_priv) >= 10)
  		mask |= VIDEO_DIP_ENABLE_DRM_GLK;
@@ -570,6 +577,7 @@ static const u8 infoframe_type_to_idx[] = {
  	HDMI_PACKET_TYPE_GENERAL_CONTROL,
  	HDMI_PACKET_TYPE_GAMUT_METADATA,
  	DP_SDP_VSC,
+	DP_SDP_ADAPTIVE_SYNC,
  	HDMI_INFOFRAME_TYPE_AVI,
  	HDMI_INFOFRAME_TYPE_SPD,
  	HDMI_INFOFRAME_TYPE_VENDOR,
@@ -1212,7 +1220,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
  	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
  		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
  		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
-		 VIDEO_DIP_ENABLE_DRM_GLK);
+		 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_ADAPTIVE_SYNC);
if (!enable) {
  		intel_de_write(dev_priv, reg, val);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..d2ab7e571e62 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -113,6 +113,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
  	struct intel_connector *connector =
  		to_intel_connector(conn_state->connector);
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
  	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
  	const struct drm_display_info *info = &connector->base.display_info;
  	int vmin, vmax;
@@ -165,6 +166,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
  	if (crtc_state->uapi.vrr_enabled) {
  		crtc_state->vrr.enable = true;
  		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+		if (drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd))
+			crtc_state->vrr.as_sdp_mode =
+						DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
  	}
  }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e00557e1a57f..c02ea07af4c2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2312,6 +2312,7 @@
   * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
   * of the infoframe structure specified by CEA-861. */
  #define   VIDEO_DIP_DATA_SIZE	32
+#define   VIDEO_DIP_ASYNC_DATA_SIZE	36
  #define   VIDEO_DIP_GMP_DATA_SIZE	36
  #define   VIDEO_DIP_VSC_DATA_SIZE	36
  #define   VIDEO_DIP_PPS_DATA_SIZE	132
@@ -2350,6 +2351,8 @@
  #define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
  #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
  #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
+/* ADL and later: */
+#define   VIDEO_DIP_ENABLE_ADAPTIVE_SYNC	REG_BIT(23)

For consistency, perhaps VIDEO_DIP_ENABLE_ADAPTIVE_SYNC_ADL would be better.

Same with others macros below.

Regards,

Ankit

/* Panel fitting */
  #define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
@@ -5040,6 +5043,7 @@
  #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
  #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
  #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
+#define	_VIDEO_DIP_AS_SDP_DATA_A	0x60484
  #define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
  #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
  #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
@@ -5054,6 +5058,7 @@
  #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
  #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
  #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
+#define	_VIDEO_DIP_AS_SDP_DATA_B	0x61484
  #define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
  #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
  #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
@@ -5083,6 +5088,9 @@
  #define GLK_TVIDEO_DIP_DRM_DATA(trans, i)	_MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
  #define ICL_VIDEO_DIP_PPS_DATA(trans, i)	_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
  #define ICL_VIDEO_DIP_PPS_ECC(trans, i)		_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
+/*ADLP and later: */
+#define TVIDEO_DIP_AS_SDP_DATA(trans, i)	_MMIO_TRANS2(trans,\
+							     _VIDEO_DIP_AS_SDP_DATA_A + (i) * 4)
#define _HSW_STEREO_3D_CTL_A 0x70020
  #define   S3D_ENABLE			(1 << 31)



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