On 21/02/2024 17:02, Paweł Anikiel wrote: > The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP > Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video > capture and Multi-Stream Transport. The user guide can be found here: > > https://www.intel.com/programmable/technical-pdfs/683273.pdf > > Signed-off-by: Paweł Anikiel <panikiel@xxxxxxxxxx> > --- > .../devicetree/bindings/media/intel,dprx.yaml | 160 ++++++++++++++++++ > 1 file changed, 160 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/intel,dprx.yaml > > diff --git a/Documentation/devicetree/bindings/media/intel,dprx.yaml b/Documentation/devicetree/bindings/media/intel,dprx.yaml > new file mode 100644 > index 000000000000..31025f2d5dcd > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/intel,dprx.yaml > @@ -0,0 +1,160 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/intel,dprx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel DisplayPort RX IP > + > +maintainers: > + - Paweł Anikiel <panikiel@xxxxxxxxxx> > + > +description: | > + The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP > + Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video > + capture and Multi-Stream Transport. > + > + The IP features a large number of configuration parameters, found at: > + https://www.intel.com/content/www/us/en/docs/programmable/683273/23-3-20-0-1/sink-parameters.html > + > + The following parameters have to be enabled: > + - Support DisplayPort sink > + - Enable GPU control > + The following parameters' values have to be set in the devicetree: > + - RX maximum link rate > + - Maximum lane count > + - Support MST > + - Max stream count (only if Support MST is enabled) > + > +properties: > + compatible: > + const: intel,dprx-20.0.1 > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + intel,max-link-rate: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Max link rate configuration parameter Please do not duplicate property name in description. It's useless. Instead explain what is this responsible for. Why max-link-rate would differ for the same dprx-20.0.1? And why standard properties cannot be used? Same for all questions below. > + > + intel,max-lane-count: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Max lane count configuration parameter > + > + intel,multi-stream-support: > + type: boolean > + description: Multi-Stream Transport support configuration parameter > + > + intel,max-stream-count: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: Max stream count configuration parameter > + > + port: > + $ref: /schemas/graph.yaml#/properties/port > + description: SST main link I don't understand why you have both port and ports. Shouldn't this be under ports? > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: MST virtual channel 0 or SST main link > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: MST virtual channel 1 > + > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: MST virtual channel 2 > + > + port@3: > + $ref: /schemas/graph.yaml#/properties/port > + description: MST virtual channel 3 > + > +required: > + - compatible > + - reg > + - interrupts > + > +allOf: > + - if: > + required: > + - intel,multi-stream-support > + then: > + required: > + - intel,max-stream-count > + - ports > + else: > + required: > + - port Best regards, Krzysztof
