On Wed, 14 Feb 2024 at 20:04, Paloma Arellano <quic_parellan@xxxxxxxxxxx> wrote:
>
> DP controller can be setup to operate in either SDP update flush mode or
> peripheral flush mode based on the DP controller hardware version.
>
> Starting in DP v1.2, the hardware documents require the use of
> peripheral flush mode for SDP packets such as PPS OR VSC SDP packets.
>
> In-line with this guidance, lets program the DP controller to use
> peripheral flush mode starting DP v1.2
>
> Changes in v3:
> - Clear up that the DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE
> macro is setting bits [24:23] to a value of 3
>
> Changes in v2:
> - Use the original dp_catalog_hw_revision() function to
> correctly check the DP HW version
>
> Signed-off-by: Paloma Arellano <quic_parellan@xxxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++
> drivers/gpu/drm/msm/dp/dp_catalog.h | 1 +
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 +
> drivers/gpu/drm/msm/dp/dp_reg.h | 5 +++++
> 4 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
> index 61d5317efe683..823eeba7e71d3 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> @@ -440,6 +440,23 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog,
> dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val);
> }
>
> +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog)
> +{
> + u32 mainlink_ctrl, hw_revision;
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> +
> + mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
> +
> + hw_revision = dp_catalog_hw_revision(dp_catalog);
> + if (hw_revision >= DP_HW_VERSION_1_2)
> + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE;
> + else
> + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP;
> +
> + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
> +}
> +
> void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
> u32 rate, u32 stream_rate_khz,
> bool fixed_nvid, bool is_ycbcr_420)
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
> index 4bf08c27a9bf3..eb05a37837beb 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.h
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
> @@ -98,6 +98,7 @@ void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config);
> void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
> void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
> void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable);
> +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog);
> void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
> void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
> u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420);
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index beef86b1aaf81..f1e7b0a5ee5d1 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -170,6 +170,7 @@ static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
>
> dp_catalog_ctrl_lane_mapping(ctrl->catalog);
> dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
> + dp_catalog_setup_peripheral_flush(ctrl->catalog);
>
> dp_ctrl_config_ctrl(ctrl);
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
> index 2983756c125cd..d4fb8572cd1e4 100644
> --- a/drivers/gpu/drm/msm/dp/dp_reg.h
> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
> @@ -6,6 +6,9 @@
> #ifndef _DP_REG_H_
> #define _DP_REG_H_
>
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +
> /* DP_TX Registers */
> #define REG_DP_HW_VERSION (0x00000000)
>
> @@ -102,6 +105,8 @@
> #define DP_MAINLINK_CTRL_ENABLE (0x00000001)
> #define DP_MAINLINK_CTRL_RESET (0x00000002)
> #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010)
> +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP (0x00800000)
This define covers data from the same bit field. Please use FIELD_PREP too.
> +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(GENMASK(24, 23), 3)
#define DP_foo_MASK GENMASK(24,23)
> #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000)
>
> #define REG_DP_STATE_CTRL (0x00000004)
> --
> 2.39.2
>
--
With best wishes
Dmitry
