On Tue, 13 Feb 2024, "Murthy, Arun R" <arun.r.murthy@xxxxxxxxx> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@xxxxxxxxx>
>> Sent: Tuesday, February 13, 2024 5:01 PM
>> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx; intel-xe@xxxxxxxxxxxxxxxxxxxxx; Nikula, Jani
>> <jani.nikula@xxxxxxxxx>; Murthy, Arun R <arun.r.murthy@xxxxxxxxx>; Ville
>> Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>> Subject: [PATCH v2 1/6] drm/mst: read sideband messaging cap
>>
>> Amend drm_dp_read_mst_cap() to return an enum, indicating "SST", "SST with
>> sideband messaging", or "MST". Modify all call sites to take the new return
>> value into account.
>>
>> v2:
>> - Rename enumerators (Ville)
>>
>> Cc: Arun R Murthy <arun.r.murthy@xxxxxxxxx>
>> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>> ---
>> drivers/gpu/drm/display/drm_dp_mst_topology.c | 20 ++++++++++------
>> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
>> drivers/gpu/drm/nouveau/nouveau_dp.c | 2 +-
>> include/drm/display/drm_dp_mst_helper.h | 23 ++++++++++++++++++-
>> 4 files changed, 38 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> b/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> index 03d528209426..c193be3577f7 100644
>> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> @@ -3608,24 +3608,30 @@ fixed20_12 drm_dp_get_vc_payload_bw(const
>> struct drm_dp_mst_topology_mgr *mgr,
>> EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
>>
>> /**
>> - * drm_dp_read_mst_cap() - check whether or not a sink supports MST
>> + * drm_dp_read_mst_cap() - Read the sink's MST mode capability
>> * @aux: The DP AUX channel to use
>> * @dpcd: A cached copy of the DPCD capabilities for this sink
>> *
>> - * Returns: %True if the sink supports MST, %false otherwise
>> + * Returns: enum drm_dp_mst_mode to indicate MST mode capability
>> */
>> -bool drm_dp_read_mst_cap(struct drm_dp_aux *aux,
>> - const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>> +enum drm_dp_mst_mode drm_dp_read_mst_cap(struct drm_dp_aux *aux,
>> + const u8
>> dpcd[DP_RECEIVER_CAP_SIZE])
>> {
>> u8 mstm_cap;
>>
>> if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_12)
>> - return false;
>> + return DRM_DP_SST;
>>
>> if (drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &mstm_cap) != 1)
>> - return false;
>> + return DRM_DP_SST;
>> +
>> + if (mstm_cap & DP_MST_CAP)
>> + return DRM_DP_MST;
>> +
>> + if (mstm_cap & DP_SINGLE_STREAM_SIDEBAND_MSG)
>> + return DRM_DP_SST_SIDEBAND_MSG;
> Bit[1] of MSTM_CAP indicates sideband messaging is supported or not
> and nothing to do with MST/SST. So would it make more sense to have it
> as DRM_DP_SIDEBAND_MSG?
Bit 1 is literally described as SINGLE_STREAM_SIDEBAND_MSG_SUPPORT in
the spec, "Supports Sideband MSG while not supporting multi-stream
transport".
Bit 1 is also only valid when bit 0 says, "Does not support MST mode".
BR,
Jani.
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>>
>> - return mstm_cap & DP_MST_CAP;
>> + return DRM_DP_SST;
>> }
>> EXPORT_SYMBOL(drm_dp_read_mst_cap);
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 5045c34a16be..a1c304f451bd 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4014,7 +4014,7 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
>>
>> return i915->display.params.enable_dp_mst &&
>> intel_dp_mst_source_support(intel_dp) &&
>> - drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
>> + drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd) ==
>> DRM_DP_MST;
>> }
>>
>> static void
>> @@ -4023,7 +4023,7 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> struct intel_encoder *encoder =
>> &dp_to_dig_port(intel_dp)->base;
>> - bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp-
>> >dpcd);
>> + bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux,
>> +intel_dp->dpcd) == DRM_DP_MST;
>>
>> drm_dbg_kms(&i915->drm,
>> "[ENCODER:%d:%s] MST support: port: %s, sink: %s,
>> modparam: %s\n", diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c
>> b/drivers/gpu/drm/nouveau/nouveau_dp.c
>> index 7de7707ec6a8..fb06ee17d9e5 100644
>> --- a/drivers/gpu/drm/nouveau/nouveau_dp.c
>> +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
>> @@ -181,7 +181,7 @@ nouveau_dp_probe_dpcd(struct nouveau_connector
>> *nv_connector,
>> if (nouveau_mst) {
>> mstm = outp->dp.mstm;
>> if (mstm)
>> - mstm->can_mst = drm_dp_read_mst_cap(aux, dpcd);
>> + mstm->can_mst = drm_dp_read_mst_cap(aux, dpcd)
>> == DRM_DP_MST;
>> }
>>
>> if (nouveau_dp_has_sink_count(connector, outp)) { diff --git
>> a/include/drm/display/drm_dp_mst_helper.h
>> b/include/drm/display/drm_dp_mst_helper.h
>> index 9b19d8bd520a..3c9e128c444a 100644
>> --- a/include/drm/display/drm_dp_mst_helper.h
>> +++ b/include/drm/display/drm_dp_mst_helper.h
>> @@ -818,7 +818,28 @@ int drm_dp_mst_topology_mgr_init(struct
>> drm_dp_mst_topology_mgr *mgr,
>>
>> void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr
>> *mgr);
>>
>> -bool drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8
>> dpcd[DP_RECEIVER_CAP_SIZE]);
>> +/**
>> + * enum drm_dp_mst_mode - sink's MST mode capability */ enum
>> +drm_dp_mst_mode {
>> + /**
>> + * @DRM_DP_SST: The sink does not support MST nor single stream
>> sideband
>> + * messaging.
>> + */
>> + DRM_DP_SST,
>> + /**
>> + * @DRM_DP_MST: Sink supports MST, more than one stream and
>> single
>> + * stream sideband messaging.
>> + */
>> + DRM_DP_MST,
>> + /**
>> + * @DRM_DP_SST_SIDEBAND_MSG: Sink supports only one stream and
>> single
>> + * stream sideband messaging.
>> + */
>> + DRM_DP_SST_SIDEBAND_MSG,
>> +};
>> +
>> +enum drm_dp_mst_mode drm_dp_read_mst_cap(struct drm_dp_aux *aux,
>> const
>> +u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>> int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr
>> *mgr, bool mst_state);
>>
>> int drm_dp_mst_hpd_irq_handle_event(struct drm_dp_mst_topology_mgr
>> *mgr,
>> --
>> 2.39.2
>
--
Jani Nikula, Intel
