The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video capture and Multi-Stream Transport. The user guide can be found here: https://www.intel.com/programmable/technical-pdfs/683273.pdf Signed-off-by: Paweł Anikiel <panikiel@xxxxxxxxxx> --- .../devicetree/bindings/media/intel,dprx.yaml | 125 ++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/intel,dprx.yaml diff --git a/Documentation/devicetree/bindings/media/intel,dprx.yaml b/Documentation/devicetree/bindings/media/intel,dprx.yaml new file mode 100644 index 000000000000..3ed37e0a4a94 --- /dev/null +++ b/Documentation/devicetree/bindings/media/intel,dprx.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/intel,dprx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel DisplayPort RX IP + +maintainers: + - Paweł Anikiel <panikiel@xxxxxxxxxx> + +properties: + compatible: + const: intel,dprx + + reg: + items: + - description: core registers + - description: irq registers + + interrupts: + maxItems: 1 + + intel,has-mst: + type: boolean + description: The device supports Multi-Stream Transport + + port: + $ref: /schemas/graph.yaml#/properties/port + description: SST main link + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 0 or SST main link + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 1 + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 2 + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 3 + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + required: + - intel,has-mst + then: + required: + - ports + else: + required: + - port + +additionalProperties: false + +examples: + - | + dprx@c0062000 { + compatible = "intel,dprx"; + reg = <0xc0062000 0x800>, + <0xc0060f80 0x10>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + intel,has-mst; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dprx_mst_0: endpoint { + remote-endpoint = <&fb_mst0_0>; + }; + }; + + port@1 { + reg = <1>; + dprx_mst_1: endpoint { + remote-endpoint = <&fb_mst1_0>; + }; + }; + + port@2 { + reg = <2>; + dprx_mst_2: endpoint { + remote-endpoint = <&fb_mst2_0>; + }; + }; + + port@3 { + reg = <3>; + dprx_mst_3: endpoint { + remote-endpoint = <&fb_mst3_0>; + }; + }; + }; + }; + + - | + dprx@c0064000 { + compatible = "intel,dprx"; + reg = <0xc0064000 0x800>, + <0xc0060fe0 0x10>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + + port { + dprx_sst_0: endpoint { + remote-endpoint = <&fb_sst_0>; + }; + }; + }; -- 2.43.0.687.g38aa6559b0-goog
