> -----Original Message-----
> From: dri-devel <dri-devel-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Imre
> Deak
> Sent: Tuesday, January 23, 2024 3:59 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 05/19] drm/i915/dp: Factor out intel_dp_config_required_rate()
>
> Factor out intel_dp_config_required_rate() used by a follow-up patch enabling the
> DP tunnel BW allocation mode.
Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++--------------
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> 2 files changed, 20 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index c7b06a9b197cc..0a5c60428ffb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2338,6 +2338,17 @@ intel_dp_compute_config_limits(struct intel_dp
> *intel_dp,
> limits);
> }
>
> +int intel_dp_config_required_rate(const struct intel_crtc_state
> +*crtc_state) {
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + int bpp = crtc_state->dsc.compression_enable ?
> + to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
> + crtc_state->pipe_bpp;
> +
> + return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); }
> +
> static int
> intel_dp_compute_link_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config, @@ -2405,31
> +2416,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> return ret;
> }
>
> - if (pipe_config->dsc.compression_enable) {
> - drm_dbg_kms(&i915->drm,
> - "DP lane count %d clock %d Input bpp %d Compressed
> bpp " BPP_X16_FMT "\n",
> - pipe_config->lane_count, pipe_config->port_clock,
> - pipe_config->pipe_bpp,
> - BPP_X16_ARGS(pipe_config-
> >dsc.compressed_bpp_x16));
> + drm_dbg_kms(&i915->drm,
> + "DP lane count %d clock %d bpp input %d compressed "
> BPP_X16_FMT " link rate required %d available %d\n",
> + pipe_config->lane_count, pipe_config->port_clock,
> + pipe_config->pipe_bpp,
> + BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
> + intel_dp_config_required_rate(pipe_config),
> + drm_dp_max_dprx_data_rate(pipe_config->port_clock,
> + pipe_config->lane_count));
>
> - drm_dbg_kms(&i915->drm,
> - "DP link rate required %i available %i\n",
> - intel_dp_link_required(adjusted_mode->crtc_clock,
> -
> to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
> - drm_dp_max_dprx_data_rate(pipe_config-
> >port_clock,
> - pipe_config->lane_count));
> - } else {
> - drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp
> %d\n",
> - pipe_config->lane_count, pipe_config->port_clock,
> - pipe_config->pipe_bpp);
> -
> - drm_dbg_kms(&i915->drm,
> - "DP link rate required %i available %i\n",
> - intel_dp_link_required(adjusted_mode->crtc_clock,
> - pipe_config->pipe_bpp),
> - drm_dp_max_dprx_data_rate(pipe_config-
> >port_clock,
> - pipe_config->lane_count));
> - }
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 46f79747f807d..37274e3c2902f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -102,6 +102,7 @@ void intel_dp_mst_suspend(struct drm_i915_private
> *dev_priv); void intel_dp_mst_resume(struct drm_i915_private *dev_priv); int
> intel_dp_max_link_rate(struct intel_dp *intel_dp); int
> intel_dp_max_lane_count(struct intel_dp *intel_dp);
> +int intel_dp_config_required_rate(const struct intel_crtc_state
> +*crtc_state);
> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
>
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> --
> 2.39.2
