The vendor kernel sets a previously unknown clock gating bit in the VIVS_PM_MODULE_CONTROLS register to disable SH_EU clock gating. Import new headers from rnndb for the definition and set the bit for the VIPNano-Si+ NPU on i.MX8MP and other affected cores. Signed-off-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> --- Changes in v2: - Add patch to turn etnaviv_is_model_rev() into a function. - Use model numbers instead of made up GCxxxx model names. - Also disable SH_EU clock gating on other models/revisions listed in the vendor kernel. - Link to v1: https://lore.kernel.org/r/20240124-etnaviv-npu-v1-0-a5aaf64aec65@xxxxxxxxxxxxxx --- Philipp Zabel (3): drm/etnaviv: Update hardware headers from rnndb drm/etnaviv: Turn etnaviv_is_model_rev() into a function drm/etnaviv: Disable SH_EU clock gating on VIPNano-Si+ drivers/gpu/drm/etnaviv/cmdstream.xml.h | 52 ++++++++++++++-- drivers/gpu/drm/etnaviv/common.xml.h | 12 ++-- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 72 +++++++++++++---------- drivers/gpu/drm/etnaviv/state.xml.h | 101 +++++++++++++++++++++++++++----- drivers/gpu/drm/etnaviv/state_blt.xml.h | 20 +++---- drivers/gpu/drm/etnaviv/state_hi.xml.h | 28 +++++---- 6 files changed, 210 insertions(+), 75 deletions(-) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20240124-etnaviv-npu-627f6881322c Best regards, -- Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
