On Tue Dec 19, 2023 at 4:39 PM CET, Luca Weiss wrote:
> On Sun Dec 3, 2023 at 1:32 AM CET, Dmitry Baryshkov wrote:
> > Enable WB2 hardware block, enabling writeback support on this platform.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
>
> Hi Dmitry,
>
> I've tried this on sm7225-fairphone-fp4 but having trouble testing this.
>
> I guess I'm using some ID wrong with modetest, could you check and see
> what I do wrong?
>
> libdrm is on version 2.4.118 from Alpine Linux/postmarketOS, kernel is
> v6.7.0-rc6 plus a few patches for hardware enablement (like display).
>
> See log:
>
> <snip>
>
Hi Dmitry,
I've tested again now and made it work.
$ modetest -M msm -a -s 38@64:1024x768 -o test.d -P 45@64:1024x768
Then display the image with
$ magick display -size 1024x768 -depth 8 RGBA:test.d
As discussed on IRC it seems the byte order of R and B might be wrong,
so it looks like BGRA is the format we get the data in, not RGBA.
Anyways:
Tested-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
Regards
Luca
>
> Regards
> Luca
>
>
> > ---
> > .../drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> > index 62db84bd15f2..3c179a73c030 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> > @@ -27,6 +27,7 @@ static const struct dpu_mdp_cfg sm6350_mdp = {
> > [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> > [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> > [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> > + [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
> > [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> > },
> > };
> > @@ -146,6 +147,21 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
> > },
> > };
> >
> > +static const struct dpu_wb_cfg sm6350_wb[] = {
> > + {
> > + .name = "wb_2", .id = WB_2,
> > + .base = 0x65000, .len = 0x2c8,
> > + .features = WB_SM8250_MASK,
> > + .format_list = wb2_formats,
> > + .num_formats = ARRAY_SIZE(wb2_formats),
> > + .clk_ctrl = DPU_CLK_CTRL_WB2,
> > + .xin_id = 6,
> > + .vbif_idx = VBIF_RT,
> > + .maxlinewidth = 1920,
> > + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
> > + },
> > +};
> > +
> > static const struct dpu_intf_cfg sm6350_intf[] = {
> > {
> > .name = "intf_0", .id = INTF_0,
> > @@ -219,6 +235,8 @@ const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> > .dsc = sm6350_dsc,
> > .pingpong_count = ARRAY_SIZE(sm6350_pp),
> > .pingpong = sm6350_pp,
> > + .wb_count = ARRAY_SIZE(sm6350_wb),
> > + .wb = sm6350_wb,
> > .intf_count = ARRAY_SIZE(sm6350_intf),
> > .intf = sm6350_intf,
> > .vbif_count = ARRAY_SIZE(sdm845_vbif),
