Add few missing pieces to support ZynqMP DPSUB live video in mode.
ZynqMP DPSUB supports 2 modes of operations in regard to video data
input.
In the first mode, DPSUB uses DMA engine to pull video data from memory
buffers. To support this the driver implements CRTC and DRM bridge
representing DP encoder.
In the second mode, DPSUB acquires video data pushed from FPGA and
passes it downstream to DP output. This mode of operation is modeled in
the driver as a DRM bridge that should be attached to some external
CRTC.
Patches 1/5,2/5,3/5,4/5 are minor fixes.
DPSUB requires input live video format to be configured.
Patch 5/5: The DP Subsystem requires the input live video format to be
configured. In this patch, we are assuming that the CRTC's bus format is
fixed (typical for FPGA CRTC) and comes from the device tree. This is a
proposed solution, as there is no API to query CRTC output bus format
or negotiate it in any other way.
Changes in v2:
- Address reviewers' comments:
- More elaborate and consistent comments / commit messages
- Fix includes' order
- Replace of_property_read_u32_index() with of_property_read_u32()
Changes in v3:
- Split patch #3 into 3) moving status register clear immediately after
read; 4) masking status against interrupts' mask
Link to v1: https://lore.kernel.org/all/20240112234222.913138-1-anatoliy.klymenko@xxxxxxx/
Link to v2: https://lore.kernel.org/all/20240119055437.2549149-1-anatoliy.klymenko@xxxxxxx/
Anatoliy Klymenko (5):
drm: xlnx: zynqmp_dpsub: Make drm bridge discoverable
drm: xlnx: zynqmp_dpsub: Fix timing for live mode
drm: xlnx: zynqmp_dpsub: Clear status register ASAP
drm: xlnx: zynqmp_dpsub: Filter interrupts against mask
drm: xlnx: zynqmp_dpsub: Set live video in format
drivers/gpu/drm/xlnx/zynqmp_disp.c | 111 +++++++++++++++++++++---
drivers/gpu/drm/xlnx/zynqmp_disp.h | 3 +-
drivers/gpu/drm/xlnx/zynqmp_disp_regs.h | 8 +-
drivers/gpu/drm/xlnx/zynqmp_dp.c | 16 +++-
drivers/gpu/drm/xlnx/zynqmp_kms.c | 2 +-
5 files changed, 119 insertions(+), 21 deletions(-)
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2.25.1
