On Thu, 18 Jan 2024 23:02:31 +0100, Marek Vasut wrote:
> According to new configuration spreadsheet from Toshiba for TC9595,
> the Pixel PLL input clock have to be in range 6..40 MHz. The sheet
> calculates those PLL input clock as reference clock divided by both
> pre-dividers. Add the extra limit.
>
>
Applied, thanks!
[1/1] drm/bridge: tc358767: Limit the Pixel PLL input range
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=f86ae204bec4
Rob
