Renesas SH series and compatible ISA CPUs. Signed-off-by: Yoshinori Sato <ysato@xxxxxxxxxxxxxxxxxxxx> --- .../devicetree/bindings/sh/cpus.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml diff --git a/Documentation/devicetree/bindings/sh/cpus.yaml b/Documentation/devicetree/bindings/sh/cpus.yaml new file mode 100644 index 000000000000..c04f897d2c2a --- /dev/null +++ b/Documentation/devicetree/bindings/sh/cpus.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sh/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH CPUs + +maintainers: + - Yoshinori Sato <ysato@xxxxxxxxxxxxxxxxxxxx> + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + +properties: + compatible: + anyOf: + - items: + - enum: + - renesas,sh2a + - renesas,sh3 + - renesas,sh4 + - renesas,sh4a + - jcore,j2 + - const: renesas,sh2 + - const: renesas,sh2 + + clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU core clock frequency. + + clocks: + maxItems: 1 + + clock-names: true + + reg: + maxItems: 1 + + device_type: true + +required: + - compatible + - reg + - device_type + +additionalProperties: true + +examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; +... -- 2.39.2
