Re: [PATCH v3 2/7] drm/bridge: tc358767: Fix order of register defines

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On Tue, Dec 12, 2023 at 8:53 AM Alexander Stein
<alexander.stein@xxxxxxxxxxxxxxx> wrote:
>
> 0x0510 is bigger than 0x50c, order them accordingly.
> No functional change intended.
>
> Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 258eacb4125a4..ab0710a35d3d1 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -116,13 +116,6 @@
>  /* System */
>  #define TC_IDREG               0x0500
>  #define SYSSTAT                        0x0508
> -#define SYSCTRL                        0x0510
> -#define DP0_AUDSRC_NO_INPUT            (0 << 3)
> -#define DP0_AUDSRC_I2S_RX              (1 << 3)
> -#define DP0_VIDSRC_NO_INPUT            (0 << 0)
> -#define DP0_VIDSRC_DSI_RX              (1 << 0)
> -#define DP0_VIDSRC_DPI_RX              (2 << 0)
> -#define DP0_VIDSRC_COLOR_BAR           (3 << 0)
>  #define SYSRSTENB              0x050c
>  #define ENBI2C                         (1 << 0)
>  #define ENBLCD0                                (1 << 2)
> @@ -130,6 +123,13 @@
>  #define ENBDSIRX                       (1 << 4)
>  #define ENBREG                         (1 << 5)
>  #define ENBHDCP                                (1 << 8)
> +#define SYSCTRL                        0x0510  /* System Control Register */
> +#define DP0_AUDSRC_NO_INPUT            (0 << 3)
> +#define DP0_AUDSRC_I2S_RX              (1 << 3)
> +#define DP0_VIDSRC_NO_INPUT            (0 << 0)
> +#define DP0_VIDSRC_DSI_RX              (1 << 0)
> +#define DP0_VIDSRC_DPI_RX              (2 << 0)
> +#define DP0_VIDSRC_COLOR_BAR           (3 << 0)
>  #define GPIOM                  0x0540
>  #define GPIOC                  0x0544
>  #define GPIOO                  0x0548
> --
> 2.34.1
>

Reviewed-by: Robert Foss <rfoss@xxxxxxxxxx>




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