Re: [Intel-gfx] [PATCH v3 02/11] drm/dp_mst: Fix PBN divider calculation for UHBR rates

[Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>]

On 2023-11-17 20:40, Rodrigo Vivi wrote:
> On Fri, Nov 17, 2023 at 06:21:07PM +0200, Ville Syrjälä wrote:
> > On Fri, Nov 17, 2023 at 05:09:27PM +0200, Imre Deak wrote:
> > > The current way of calculating the pbn_div value, the link BW per each
> > > MTP slot, worked only for DP 1.4 link rates. Fix things up for UHBR
> > > rates calculating with the correct channel coding efficiency based on
> > > the link rate.
> > >
> > > v2:
> > > - Return the fractional pbn_div value from drm_dp_get_vc_payload_bw().
> > > v3:
> > > - Fix rounding up quotient while calculating req_slots. (Ville)
> > >
> > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > > Cc: Lyude Paul <lyude@xxxxxxxxxx>
> > > Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
> > > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> >
> > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Dave, Sima, it looks like this whole series is ready for getting merged:
>
> https://patchwork.freedesktop.org/series/126526/
>
> But it has these 3 drm/dp_mst here.
> Ack to merge them through drm-intel?
Well, as drm-misc maintainer:

Acked-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>

> > > ---
> > >   drivers/gpu/drm/display/drm_dp_mst_topology.c | 10 +++++++---
> > >   include/drm/display/drm_dp_helper.h           | 13 +++++++++++++
> > >   2 files changed, 20 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > index 000d05e80352a..8ca01a6bf645d 100644
> > > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > @@ -3585,14 +3585,18 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
> > >   fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
> > >   				    int link_rate, int link_lane_count)
> > >   {
> > > +	int ch_coding_efficiency =
> > > +		drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate));
> > >   	fixed20_12 ret;
> > >   
> > >   	if (link_rate == 0 || link_lane_count == 0)
> > >   		drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n",
> > >   			    link_rate, link_lane_count);
> > >   
> > > -	/* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
> > > -	ret.full = dfixed_const(link_rate * link_lane_count / 54000);
> > > +	/* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
> > > +	ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,
> > > +						  ch_coding_efficiency),
> > > +				      (1000000ULL * 8 * 5400) >> 12);
> > >   
> > >   	return ret;
> > >   }
> > > @@ -4342,7 +4346,7 @@ int drm_dp_atomic_find_time_slots(struct drm_atomic_state *state,
> > >   		}
> > >   	}
> > >   
> > > -	req_slots = DIV_ROUND_UP(pbn, dfixed_trunc(topology_state->pbn_div));
> > > +	req_slots = DIV_ROUND_UP(dfixed_const(pbn), topology_state->pbn_div.full);
> > >   
> > >   	drm_dbg_atomic(mgr->dev, "[CONNECTOR:%d:%s] [MST PORT:%p] TU %d -> %d\n",
> > >   		       port->connector->base.id, port->connector->name,
> > > diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> > > index c5f1079acb3b1..863b2e7add29e 100644
> > > --- a/include/drm/display/drm_dp_helper.h
> > > +++ b/include/drm/display/drm_dp_helper.h
> > > @@ -252,6 +252,19 @@ drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
> > >   	return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
> > >   }
> > >   
> > > +/**
> > > + * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR
> > > + * @link_rate: link rate in 10kbits/s units
> > > + *
> > > + * Determine if the provided link rate is an UHBR rate.
> > > + *
> > > + * Returns: %True if @link_rate is an UHBR rate.
> > > + */
> > > +static inline bool drm_dp_is_uhbr_rate(int link_rate)
> > > +{
> > > +	return link_rate >= 1000000;
> > > +}
> > > +
> > >   /*
> > >    * DisplayPort AUX channel
> > >    */
> > > --
> > > 2.39.2
> >
> > --
> > Ville Syrjälä
> > Intel