Re: [Freedreno] [PATCH v2] drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy

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On 11/16/2023 12:36 PM, Abhinav Kumar wrote:


On 11/9/2023 4:02 PM, Jonathan Marek wrote:
Use the same value as the downstream driver. This change is needed for CPHY
mode to work correctly.

Fixes: 8b034e6771113 ("drm/msm/dsi: add support for DSI-PHY on SM8550")

One error here. We need 12 chars of SHA but you have 13 otherwise checkpatch cries

Fixes: 8b034e677111 ("drm/msm/dsi: add support for DSI-PHY on SM8550")

Will fix this up while applying.

Signed-off-by: Jonathan Marek <jonathan@xxxxxxxx>
---
v2: fixed the Fixes: line

  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)


Good catch !

LGTM

Reviewed-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 3b1ed02f644d..89a6344bc865 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -918,7 +918,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
      if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
          if (phy->cphy_mode) {
              vreg_ctrl_0 = 0x45;
-            vreg_ctrl_1 = 0x45;
+            vreg_ctrl_1 = 0x41;
              glbl_rescode_top_ctrl = 0x00;
              glbl_rescode_bot_ctrl = 0x00;
          } else {



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