We'll have to enable the VGA functionality for detecting the ast device type. Make this work without an instance of the ast device. Signed-off-by: Thomas Zimmermann <tzimmermann@xxxxxxx> Reviewed-by: Jocelyn Falempe <jfalempe@xxxxxxxxxx> --- drivers/gpu/drm/ast/ast_main.c | 29 ++++++++++++----------------- drivers/gpu/drm/ast/ast_reg.h | 9 +++++++-- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 026ef893dd509..82fcee967d984 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -35,22 +35,17 @@ #include "ast_drv.h" -static bool ast_is_vga_enabled(struct drm_device *dev) +static bool ast_is_vga_enabled(void __iomem *ioregs) { - struct ast_device *ast = to_ast_device(dev); - u8 ch; - - ch = ast_io_read8(ast, AST_IO_VGAER); + u8 vgaer = __ast_read8(ioregs, AST_IO_VGAER); - return !!(ch & 0x01); + return vgaer & AST_IO_VGAER_VGA_ENABLE; } -static void ast_enable_vga(struct drm_device *dev) +static void ast_enable_vga(void __iomem *ioregs) { - struct ast_device *ast = to_ast_device(dev); - - ast_io_write8(ast, AST_IO_VGAER, 0x01); - ast_io_write8(ast, AST_IO_VGAMR_W, 0x01); + __ast_write8(ioregs, AST_IO_VGAER, AST_IO_VGAER_VGA_ENABLE); + __ast_write8(ioregs, AST_IO_VGAMR_W, AST_IO_VGAMR_IOSEL); } /* @@ -74,9 +69,9 @@ static int ast_enable_mmio(struct ast_device *ast) return devm_add_action_or_reset(dev->dev, ast_enable_mmio_release, ast); } -static void ast_open_key(struct ast_device *ast) +static void ast_open_key(void __iomem *ioregs) { - ast_set_index_reg(ast, AST_IO_VGACRI, 0x80, 0xA8); + __ast_write8_i(ioregs, AST_IO_VGACRI, 0x80, AST_IO_VGACR80_PASSWORD); } static int ast_device_config_init(struct ast_device *ast) @@ -487,7 +482,7 @@ struct ast_device *ast_device_create(const struct drm_driver *drv, ast->regs = regs; ast->ioregs = ioregs; - if (!ast_is_vga_enabled(dev)) { + if (!ast_is_vga_enabled(ioregs)) { drm_info(dev, "VGA not enabled on entry, requesting chip POST\n"); need_post = true; } @@ -497,10 +492,10 @@ struct ast_device *ast_device_create(const struct drm_driver *drv, * access to the scratch registers will fail. */ if (need_post) - ast_enable_vga(dev); - + ast_enable_vga(ioregs); /* Enable extended register access */ - ast_open_key(ast); + ast_open_key(ioregs); + ret = ast_enable_mmio(ast); if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h index 05bab94a9a906..5258a84ef3a6f 100644 --- a/drivers/gpu/drm/ast/ast_reg.h +++ b/drivers/gpu/drm/ast/ast_reg.h @@ -13,8 +13,14 @@ #define AST_IO_MM_LENGTH (128) #define AST_IO_VGAARI_W (0x40) + #define AST_IO_VGAMR_W (0x42) +#define AST_IO_VGAMR_R (0x4c) +#define AST_IO_VGAMR_IOSEL BIT(0) + #define AST_IO_VGAER (0x43) +#define AST_IO_VGAER_VGA_ENABLE BIT(0) + #define AST_IO_VGASRI (0x44) #define AST_IO_VGADRR (0x47) #define AST_IO_VGADWR (0x48) @@ -22,14 +28,13 @@ #define AST_IO_VGAGRI (0x4E) #define AST_IO_VGACRI (0x54) +#define AST_IO_VGACR80_PASSWORD (0xa8) #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ #define AST_IO_VGACRCB_HWC_ENABLED BIT(1) #define AST_IO_VGAIR1_R (0x5A) #define AST_IO_VGAIR1_VREFRESH BIT(3) -#define AST_IO_VGAMR_R (0x4C) - /* * Display Transmitter Type */ -- 2.42.0