Hi,
> -----Original Message-----
> From: Murthy, Arun R <arun.r.murthy@xxxxxxxxx>
> Sent: Wednesday, October 4, 2023 4:01 PM
> To: Manna, Animesh <animesh.manna@xxxxxxxxx>; intel-
> gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx; Nikula, Jani <jani.nikula@xxxxxxxxx>;
> Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Subject: RE: [PATCH v6 5/6] drm/i915/panelreplay: enable/disable panel
> replay
>
>
>
> > -----Original Message-----
> > From: Manna, Animesh <animesh.manna@xxxxxxxxx>
> > Sent: Thursday, September 21, 2023 11:44 AM
> > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx; Nikula, Jani
> > <jani.nikula@xxxxxxxxx>; Hogander, Jouni <jouni.hogander@xxxxxxxxx>;
> > Murthy, Arun R <arun.r.murthy@xxxxxxxxx>; Manna, Animesh
> > <animesh.manna@xxxxxxxxx>
> > Subject: [PATCH v6 5/6] drm/i915/panelreplay: enable/disable panel
> > replay
> >
> > TRANS_DP2_CTL register is programmed to enable panel replay from
> > source and sink is enabled through panel replay dpcd configuration
> address.
> >
> > Bspec: 1407940617
> >
> > v1: Initial version.
> > v2:
> > - Use pr_* flags instead psr_* flags. [Jouni]
> > - Remove intel_dp_is_edp check as edp1.5 also has panel replay.
> > [Jouni]
> >
> > v3: Cover letter updated and selective fetch condition check is added
> > before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]
> >
> > v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped.
> > [Jouni]
> >
> > v5: Added PSR2_MAN_TRK_CTL programming as needed for Continuous
> Full
> > Frame (CFF) update.
> >
> > Note: Initial plan is to enable panel replay in full-screen live
> > active frame update mode. In a incremental approach panel replay will
> > be enabled in selctive update mode if there is any gap in curent
> implementation.
> >
> > Cc: Jouni Högander <jouni.hogander@xxxxxxxxx>
> > Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +-
> > .../drm/i915/display/intel_display_types.h | 1 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 65 ++++++++++++++-----
> > 3 files changed, 56 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4668de45d6fe..203c56c5e208 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2717,10 +2717,15 @@ static void intel_ddi_pre_enable_dp(struct
> > intel_atomic_state *state,
> > const struct drm_connector_state
> > *conn_state) {
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >
> > - if (HAS_DP20(dev_priv))
> > + if (HAS_DP20(dev_priv)) {
> > intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
> > crtc_state);
> > + if (crtc_state->has_panel_replay)
> > + drm_dp_dpcd_writeb(&intel_dp->aux,
> > PANEL_REPLAY_CONFIG,
> > + DP_PANEL_REPLAY_ENABLE);
> > + }
> >
> > if (DISPLAY_VER(dev_priv) >= 14)
> > mtl_ddi_pre_enable_dp(state, encoder, crtc_state,
> conn_state); diff
> > --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 3eadd8e12f63..1cf302e9deed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1698,6 +1698,7 @@ struct intel_psr {
> > u16 su_y_granularity;
> > bool source_panel_replay_support;
> > bool sink_panel_replay_support;
> > + bool panel_replay_enabled;
> > u32 dc3co_exitline;
> > u32 dc3co_exit_delay;
> > struct delayed_work dc3co_work;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index a59f13c29c3d..67337b4a421b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -607,8 +607,11 @@ static void intel_psr_enable_sink(struct intel_dp
> > *intel_dp)
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > u8 dpcd_val = DP_PSR_ENABLE;
> >
> > - /* Enable ALPM at sink for psr2 */
> > + if (intel_dp->psr.panel_replay_enabled)
> > + return;
> > +
> > if (intel_dp->psr.psr2_enabled) {
> > + /* Enable ALPM at sink for psr2 */
> > drm_dp_dpcd_writeb(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CONFIG,
> > DP_ALPM_ENABLE |
> >
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> > @@ -758,6 +761,17 @@ static int psr2_block_count(struct intel_dp
> *intel_dp)
> > return psr2_block_count_lines(intel_dp) / 4; }
> >
> > +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) {
> Is this specific to DG2?
> If not can dg2 be replaces with intel ?
Following the naming convention followed for psr. DG2 used as it is the first platform which can support panel replay.
For example hsw_activate_psr2() done for psr2.
>
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp-
> >psr.transcoder),
> > + 0,
> > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
> > +
> > + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
> 0,
> > + TRANS_DP2_PANEL_REPLAY_ENABLE); }
> > +
> > static void hsw_activate_psr2(struct intel_dp *intel_dp) {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -
> > 1322,18 +1336,23 @@ void intel_psr_get_config(struct intel_encoder
> > *encoder,
> > return;
> >
> > intel_dp = &dig_port->dp;
> > - if (!CAN_PSR(intel_dp))
> > + if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
> > return;
> >
> > mutex_lock(&intel_dp->psr.lock);
> > if (!intel_dp->psr.enabled)
> > goto unlock;
> >
> > - /*
> > - * Not possible to read EDP_PSR/PSR2_CTL registers as it is
> > - * enabled/disabled because of frontbuffer tracking and others.
> > - */
> > - pipe_config->has_psr = true;
> > + if (intel_dp->psr.panel_replay_enabled) {
> > + pipe_config->has_panel_replay = true;
> Can you recheck this logic, If panel replay is enabled then setting the
> has_panel_replay flag.
> Rather it should be the reverse way, else you can also get the panel_replay
> availability from the dpcd registers.
Similar design followed in psr implementation.
>
> > + } else {
> > + /*
> > + * Not possible to read EDP_PSR/PSR2_CTL registers as it is
> > + * enabled/disabled because of frontbuffer tracking and
> others.
> > + */
> > + pipe_config->has_psr = true;
> > + }
> > +
> > pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
> > pipe_config->infoframes.enable |=
> > intel_hdmi_infoframe_enable(DP_SDP_VSC);
> >
> > @@ -1370,8 +1389,10 @@ static void intel_psr_activate(struct intel_dp
> > *intel_dp)
> >
> > lockdep_assert_held(&intel_dp->psr.lock);
> >
> > - /* psr1 and psr2 are mutually exclusive.*/
> > - if (intel_dp->psr.psr2_enabled)
> > + /* psr1, psr2 and panel-replay are mutually exclusive.*/
> > + if (intel_dp->psr.panel_replay_enabled)
> > + dg2_activate_panel_replay(intel_dp);
> > + else if (intel_dp->psr.psr2_enabled)
> > hsw_activate_psr2(intel_dp);
> > else
> > hsw_activate_psr1(intel_dp);
> > @@ -1549,6 +1570,7 @@ static void intel_psr_enable_locked(struct
> > intel_dp *intel_dp,
> > drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> >
> > intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > + intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
> If so then we don’t need 2 separate flags.
Similar design followed in psr implementation.
I can understand your concern but as per previous review feedback followed the psr implementation as much possible.
Regards,
Animesh
>
> > intel_dp->psr.busy_frontbuffer_bits = 0;
> > intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> > intel_dp->psr.transcoder = crtc_state->cpu_transcoder; @@ -1564,8
> > +1586,12 @@ static void intel_psr_enable_locked(struct intel_dp
> > +*intel_dp,
> > if (!psr_interrupt_error_check(intel_dp))
> > return;
> >
> > - drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> > - intel_dp->psr.psr2_enabled ? "2" : "1");
> > + if (intel_dp->psr.panel_replay_enabled)
> > + drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");
> > + else
> > + drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> > + intel_dp->psr.psr2_enabled ? "2" : "1");
> > +
> > intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
> > intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
> > intel_psr_enable_sink(intel_dp);
> > @@ -1594,7 +1620,10 @@ static void intel_psr_exit(struct intel_dp
> *intel_dp)
> > return;
> > }
> >
> > - if (intel_dp->psr.psr2_enabled) {
> > + if (intel_dp->psr.panel_replay_enabled) {
> > + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp-
> > >psr.transcoder),
> > + TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> > + } else if (intel_dp->psr.psr2_enabled) {
> > tgl_disallow_dc3co_on_psr2_exit(intel_dp);
> >
> > val = intel_de_rmw(dev_priv,
> EDP_PSR2_CTL(cpu_transcoder), @@
> > -1643,8 +1672,11 @@ static void intel_psr_disable_locked(struct
> > intel_dp
> > *intel_dp)
> > if (!intel_dp->psr.enabled)
> > return;
> >
> > - drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> > - intel_dp->psr.psr2_enabled ? "2" : "1");
> > + if (intel_dp->psr.panel_replay_enabled)
> > + drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n");
> > + else
> > + drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> > + intel_dp->psr.psr2_enabled ? "2" : "1");
> >
> > intel_psr_exit(intel_dp);
> > intel_psr_wait_exit_locked(intel_dp);
> > @@ -1677,6 +1709,7 @@ static void intel_psr_disable_locked(struct
> > intel_dp
> > *intel_dp)
> > drm_dp_dpcd_writeb(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CONFIG, 0);
> >
> > intel_dp->psr.enabled = false;
> > + intel_dp->psr.panel_replay_enabled = false;
> > intel_dp->psr.psr2_enabled = false;
> > intel_dp->psr.psr2_sel_fetch_enabled = false;
> > intel_dp->psr.psr2_sel_fetch_cff_enabled = false; @@ -2246,7
> +2279,7
> > @@ static void _intel_psr_post_plane_update(const struct
> > intel_atomic_state *state,
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_encoder *encoder;
> >
> > - if (!crtc_state->has_psr)
> > + if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
> > return;
> >
> > for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> @@
> > -2293,7 +2326,7 @@ void intel_psr_post_plane_update(const struct
> > intel_atomic_state *state)
> > struct intel_crtc *crtc;
> > int i;
> >
> > - if (!HAS_PSR(dev_priv))
> > + if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
> > return;
> >
> > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
> > --
> > 2.29.0
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
