Hi Jacopo Mondi,
Looks like you are happy with my response for V10. I will send V11 soon.
Cheers,
Biju
> -----Original Message-----
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Sent: Friday, September 8, 2023 2:24 PM
> Subject: RE: [PATCH v10 3/4] drm: renesas: Add RZ/G2L DU Support
>
> Hi Jacopo Mondi,
>
> Thanks for the review.
>
> > Subject: Re: [PATCH v10 3/4] drm: renesas: Add RZ/G2L DU Support
> >
> > Hi Biju
> >
> > On Tue, Jul 04, 2023 at 10:04:46AM +0100, Biju Das wrote:
> > > The LCD controller is composed of Frame Compression Processor (FCPVD),
> > > Video Signal Processor (VSPD), and Display Unit (DU).
> > >
> > > It has DPI/DSI interfaces and supports a maximum resolution of 1080p
> > > along with 2 RPFs to support the blending of two picture layers and
> > > raster operations (ROPs).
> > >
> > > The DU module is connected to VSPD. Add RZ/G2L DU support for RZ/G2L
> > > alike SoCs.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > ---
> > > Ref:
> > >
> > > v9->v10:
> > > * Dropped ARM64 dependency from Kconfig.
> > > * Sorted the configs alphabetically in Kconfig.
> > > * Dropped DRM_RCAR_VSP config option and make DRM_RZG2L_DU depend on
> > > VIDEO_RENESAS_VSP1.
> > > * On rzg2l_du_crtc_set_display_timing() replaced the setting of parent
> > > clk rate with dclk rate.
> > > * Added rzg2l_du_write() wrapper function.
> > > * Updated the comment atomic_begin->atomic_flush.
> > > * Dropped .atomic_check and .atomic_begin callback
> > > * Renamed __rzg2l_du_crtc_plane_atomic_check-
> > >__rzg2l_du_vsp_plane_atomic
> > > _check and moved it to rzg2l_du_vsp.c
> > > * Added struct clk in rzg2l_du_crtc.h
> > > * Dropped the variables mmio_offset,index,vblank_lock,vblank_wait,
> > > vblank_count from struct rzg2l_du_crtc.
> > > * Replaced the macro to_rzg2l_crtc with static inline functions.
> > > * Dropped the unneeded header files clk.h, io.h, mm.h, pm.h, slab.h,
> > > wait.h and drm_managed.h from rzg2l_du_drv.c.
> > > * Replaced DRM_INFO->drm_info
> > > * Dropped the callbacks prime_handle_to_fd, prime_fd_to_handle and
> > > gem_prime_mmap.
> > > * Replaced the callback remove->remove_new.
> > > * Dropped header file wait.h and added forward declarations struct clk
> > and
> > > rzg2l_du_device from rzg2l_du_drv.h.
> > > * Dropped the dsi and dpad0_source variables from struct
> > rzg2l_du_device.
> > > * Replaced the macro to_rzg2l_encoder with static inline functions.
> > > * Dropped header files dma-buf.h and wait.h from rzg2l_du_kms.c.
> > > * Dropped struct sg_table and added the scatterlist.h header file in
> > > rzg2l_du_vsp.h
> > > * Added container_of.h header file, forward declarations struct device
> > and
> > > struct rzg2l_du_device in rzg2l_du_vsp.h.
> > > v8->v9:
> > > * Dropped reset_control_assert() from error patch for
> > rzg2l_du_crtc_get() as
> > > suggested by Philipp Zabel.
> > > v7->v8:
> > > * Dropped RCar du lib and created RZ/G2L DU DRM driver by creating
> > rz_du folder.
> > > * Updated KConfig and Makefile.
> > > v6->v7:
> > > * Split DU lib and RZ/G2L du driver as separate patch series as
> > > DU support added to more platforms based on RZ/G2L alike SoCs.
> > > * Rebased to latest drm-tip.
> > > * Added patch #2 for binding support for RZ/V2L DU
> > > * Added patch #4 for driver support for RZ/V2L DU
> > > * Added patch #5 for SoC DTSI support for RZ/G2L DU
> > > * Added patch #6 for SoC DTSI support for RZ/V2L DU
> > > * Added patch #7 for Enabling DU on SMARC EVK based on RZ/{G2L,V2L}
> > SoCs.
> > > * Added patch #8 for Enabling DU on SMARC EVK based on RZ/G2LC SoC.
> > > ---
> > > diff --git a/drivers/gpu/drm/renesas/Kconfig
> > b/drivers/gpu/drm/renesas/Kconfig
> > > index 3777dad17f81..21862a8ef710 100644
> > > --- a/drivers/gpu/drm/renesas/Kconfig
> > > +++ b/drivers/gpu/drm/renesas/Kconfig
> > > @@ -1,4 +1,5 @@
> > > # SPDX-License-Identifier: GPL-2.0-only
> > >
> > > source "drivers/gpu/drm/renesas/rcar-du/Kconfig"
> > > +source "drivers/gpu/drm/renesas/rz-du/Kconfig"
> > > source "drivers/gpu/drm/renesas/shmobile/Kconfig"
> > > diff --git a/drivers/gpu/drm/renesas/Makefile
> > b/drivers/gpu/drm/renesas/Makefile
> > > index ec0e89e7a592..b8d8bc53967f 100644
> > > --- a/drivers/gpu/drm/renesas/Makefile
> > > +++ b/drivers/gpu/drm/renesas/Makefile
> > > @@ -1,4 +1,5 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > >
> > > obj-y += rcar-du/
> > > +obj-y += rz-du/
> > > obj-$(CONFIG_DRM_SHMOBILE) += shmobile/
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/Kconfig
> > b/drivers/gpu/drm/renesas/rz-du/Kconfig
> > > new file mode 100644
> > > index 000000000000..5f0db2c5fee6
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/renesas/rz-du/Kconfig
> > > @@ -0,0 +1,12 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> > > +config DRM_RZG2L_DU
> > > + tristate "DRM Support for RZ/G2L Display Unit"
> > > + depends on ARCH_RZG2L || COMPILE_TEST
> > > + depends on DRM && OF
> > > + depends on VIDEO_RENESAS_VSP1
> >
> > VIDEO_RENESAS_VSP1 is defined in drivers/media/platform/renesas/
> > while the symbol for the DRM compositor is DRM_RCAR_VSP. Just checking
>
> It is based on review feedback from Laurent for previous patch series.
> <snippet for Laurent>
> [1]
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork
> .kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20230502100912.143114-
> 5-
> biju.das.jz%40bp.renesas.com%2F&data=05%7C01%7Cbiju.das.jz%40bp.renesas.com
> %7C189ff12c869844243d8c08dbb06ef6a7%7C53d82571da1947e49cb4625a166a4a2a%7C0%
> 7C0%7C638297762872840667%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIj
> oiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=Xp9JABIt%2FA
> gE%2B%2BFMykCDFOkv0gVkvrV9eeLOfrprEcw%3D&reserved=0
>
> This duplicates the config symbol in
> drivers/gpu/drm/renesas/rcar-du/Kconfig.
>
> Unlike on R-Car, where some SoC generations can operate without the VSP,
> RZ/G2L requires the VSP. You can drop this configuration option and just
> make DRM_RZG2L_DU depend on VIDEO_RENESAS_VSP1.
>
>
> > this is intentional, as reading the previous iteration of the series
> > my understanding is that the RZG2L and R-Car VSP units are the same ?
>
> RZ/G2L VSP is identical to R-Car V3M.
>
> >
> > > + select DRM_GEM_DMA_HELPER
> > > + select DRM_KMS_HELPER
> > > + select VIDEOMODE_HELPERS
> > > + help
> > > + Choose this option if you have an RZ/G2L alike chipset.
> > > + If M is selected the module will be called rzg2l-du-drm.
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/Makefile
> > b/drivers/gpu/drm/renesas/rz-du/Makefile
> > > new file mode 100644
> > > index 000000000000..2cdf3ccd0459
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/renesas/rz-du/Makefile
> > > @@ -0,0 +1,8 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> > > +rzg2l-du-drm-y := rzg2l_du_crtc.o \
> > > + rzg2l_du_drv.o \
> > > + rzg2l_du_encoder.o \
> > > + rzg2l_du_kms.o \
> > > +
> > > +rzg2l-du-drm-$(CONFIG_DRM_RCAR_VSP) += rzg2l_du_vsp.o
> >
> >
> > Sorry if I'm asking questions that have already been clarified in
> > previous version, but I see the same Kconfig symbol used to select two
> > different drivers in drivers/gpu/drm/renesas/rz-du/Makefile and
> > drivers/gpu/drm/renesas/rcar-du/Makefile
> >
> >
> > rzg2l-du-drm-$(CONFIG_DRM_RCAR_VSP) += rzg2l_du_vsp.o
> > rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
> >
> > Is this ok ? I see
> >
> > config DRM_RCAR_VSP
> > ..
> > depends on DRM_RCAR_DU
> >
> > so it seems to me you can get rzg2l_du_vsp.o only if you select
> > DRM_RCAR_DU,
> > something which shouldn't be needed for RZ/G2L, right ?
>
> Oops missed it, it should be CONFIG_VIDEO_RENESAS_VSP1.
>
> rzg2l-du-drm-$(CONFIG_VIDEO_RENESAS_VSP1) += rzg2l_du_vsp.o
>
> >
> >
> > > +obj-$(CONFIG_DRM_RZG2L_DU) += rzg2l-du-drm.o
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
> > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
> > > new file mode 100644
> > > index 000000000000..5765bf55ff26
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
> > > @@ -0,0 +1,599 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * RZ/G2L Display Unit CRTCs
> > > + *
> > > + * Copyright (C) 2023 Renesas Electronics Corporation
> > > + *
> > > + * Based on rcar_du_crtc.c
> > > + */
> > > +
> > > +#include <linux/clk.h>
> > > +#include <linux/mutex.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/reset.h>
> > > +
> > > +#include <drm/drm_atomic.h>
> > > +#include <drm/drm_atomic_helper.h>
> > > +#include <drm/drm_bridge.h>
> > > +#include <drm/drm_crtc.h>
> > > +#include <drm/drm_device.h>
> > > +#include <drm/drm_framebuffer.h>
> > > +#include <drm/drm_gem_dma_helper.h>
> > > +#include <drm/drm_vblank.h>
> > > +
> > > +#include "rzg2l_du_crtc.h"
> > > +#include "rzg2l_du_drv.h"
> > > +#include "rzg2l_du_encoder.h"
> > > +#include "rzg2l_du_kms.h"
> > > +#include "rzg2l_du_vsp.h"
> > > +#include "rzg2l_du_regs.h"
> > > +
> > > +static inline void rzg2l_du_write(struct rzg2l_du_device *rcdu, u32
> > reg, u32 data)
> > > +{
> > > + writel(data, rcdu->mmio + reg);
> > > +}
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Hardware Setup
> > > + */
> > > +
> > > +static void rzg2l_du_crtc_set_display_timing(struct rzg2l_du_crtc
> > *rcrtc)
> > > +{
> > > + const struct drm_display_mode *mode = &rcrtc->crtc.state-
> > >adjusted_mode;
> > > + struct rzg2l_du_device *rcdu = rcrtc->dev;
> > > + unsigned long mode_clock = mode->clock * 1000;
> > > + u32 ditr0, ditr1, ditr2, ditr3, ditr4, ditr5, pbcr0;
> > > +
> > > + clk_prepare_enable(rcrtc->rzg2l_clocks.dclk);
> > > + clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock);
> >
> > I read
> > The duty of this clock is 50% when the display parallel interface
> >
> > Is this supported ?
>
> Current driver doesn't support DPI. There is a plan to add it later.
>
> The plan is to detect DSI or DPI from device tree and update the PLL
> generation similar to DSI to support DPI clock rates, as the PLL parameters
> for DSI and DPI are different.
>
> RZ/G2L SMARC EVK doesn't have DPI interface.
> But RZ/G2UL SMARC EVK supports DPI.
>
> >
> > > +
> > > + ditr0 = (DU_DITR0_DEMD_HIGH
> >
> > I see most registers definition in rzg2l_du_regs.h being only used by
> > the crtc driver (some of them are not even used). Why a separate
> > header file ?
>
> For consistency I added header file similar to R-Car. Please let me know
> this to be added in .c ?
>
> >
> > > + | ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DU_DITR0_VSPOL : 0)
> > > + | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DU_DITR0_HSPOL :
> > 0));
> > > +
> > > + ditr1 = DU_DITR1_VSA(mode->vsync_end - mode->vsync_start)
> > > + | DU_DITR1_VACTIVE(mode->vdisplay);
> > > +
> > > + ditr2 = DU_DITR2_VBP(mode->vtotal - mode->vsync_end)
> > > + | DU_DITR2_VFP(mode->vsync_start - mode->vdisplay);
> > > +
> > > + ditr3 = DU_DITR3_HSA(mode->hsync_end - mode->hsync_start)
> > > + | DU_DITR3_HACTIVE(mode->hdisplay);
> > > +
> > > + ditr4 = DU_DITR4_HBP(mode->htotal - mode->hsync_end)
> > > + | DU_DITR4_HFP(mode->hsync_start - mode->hdisplay);
> > > +
> > > + ditr5 = DU_DITR5_VSFT(0) | DU_DITR5_HSFT(0);
> >
> > Weird, not documented in TRM "R01UH0914EJ0130, May 12, 2023, Rev.1.30"
>
> Latest HW manual deleted this register. Please see change history. I will
> remove ditr5.
>
> 2691 Table 33.8 DU Register Configuration: DU Display I/F Timing Register
> 5, deleted.
>
> >
> > > +
> > > + pbcr0 = DU_PBCR0_PB_DEP(0x1f);
> > > +
> > > + rzg2l_du_write(rcdu, DU_DITR0, ditr0);
> > > + rzg2l_du_write(rcdu, DU_DITR1, ditr1);
> > > + rzg2l_du_write(rcdu, DU_DITR2, ditr2);
> > > + rzg2l_du_write(rcdu, DU_DITR3, ditr3);
> > > + rzg2l_du_write(rcdu, DU_DITR4, ditr4);
> > > + rzg2l_du_write(rcdu, DU_DITR5, ditr5);
> > > + rzg2l_du_write(rcdu, DU_PBCR0, pbcr0);
> > > +
> > > + /* Enable auto resume when underrun */
> > > + rzg2l_du_write(rcdu, DU_MCR1, DU_MCR1_PB_AUTOCLR);
> >
> > I can't immediately relate this setting with "auto-resume"
> >
> > PB_AUTOCLR 1: Clear during blanking (according DU_MCR1.OPMD)
> > OPMD: 0: After frame end, LIFC wait, and PBUF pointers are
> > cleared if
> > DU_MCR1.PB_AUTOCLR is set to “1”
> >
> > Could you clarify this ?
>
> OK, I will update the comment as auto-clear to be consistent with HW
> manual.
>
> >
> > > +}
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Page Flip
> > > + */
> > > +
> > > +void rzg2l_du_crtc_finish_page_flip(struct rzg2l_du_crtc *rcrtc)
> > > +{
> > > + struct drm_pending_vblank_event *event;
> > > + struct drm_device *dev = rcrtc->crtc.dev;
> > > + unsigned long flags;
> > > +
> > > + spin_lock_irqsave(&dev->event_lock, flags);
> > > + event = rcrtc->event;
> > > + rcrtc->event = NULL;
> > > + spin_unlock_irqrestore(&dev->event_lock, flags);
> > > +
> > > + if (!event)
> > > + return;
> > > +
> > > + spin_lock_irqsave(&dev->event_lock, flags);
> > > + drm_crtc_send_vblank_event(&rcrtc->crtc, event);
> > > + wake_up(&rcrtc->flip_wait);
> > > + spin_unlock_irqrestore(&dev->event_lock, flags);
> > > +
> > > + drm_crtc_vblank_put(&rcrtc->crtc);
> > > +}
> > > +
> > > +static bool rzg2l_du_crtc_page_flip_pending(struct rzg2l_du_crtc
> > *rcrtc)
> > > +{
> > > + struct drm_device *dev = rcrtc->crtc.dev;
> > > + unsigned long flags;
> > > + bool pending;
> > > +
> > > + spin_lock_irqsave(&dev->event_lock, flags);
> > > + pending = rcrtc->event;
> > > + spin_unlock_irqrestore(&dev->event_lock, flags);
> > > +
> > > + return pending;
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_wait_page_flip(struct rzg2l_du_crtc *rcrtc)
> > > +{
> > > + struct rzg2l_du_device *rcdu = rcrtc->dev;
> > > +
> > > + if (wait_event_timeout(rcrtc->flip_wait,
> > > + !rzg2l_du_crtc_page_flip_pending(rcrtc),
> > > + msecs_to_jiffies(50)))
> > > + return;
> > > +
> > > + dev_warn(rcdu->dev, "page flip timeout\n");
> > > +
> > > + rzg2l_du_crtc_finish_page_flip(rcrtc);
> > > +}
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Start/Stop and Suspend/Resume
> > > + */
> > > +
> > > +static void rzg2l_du_crtc_setup(struct rzg2l_du_crtc *rcrtc)
> > > +{
> > > + /* Configure display timings and output routing */
> > > + rzg2l_du_crtc_set_display_timing(rcrtc);
> > > +
> > > + /* Enable the VSP compositor. */
> > > + rzg2l_du_vsp_enable(rcrtc);
> > > +
> > > + /* Turn vertical blanking interrupt reporting on. */
> > > + drm_crtc_vblank_on(&rcrtc->crtc);
> > > +}
> > > +
> > > +static int rzg2l_du_crtc_get(struct rzg2l_du_crtc *rcrtc)
> > > +{
> > > + int ret;
> > > +
> > > + /*
> > > + * Guard against double-get, as the function is called from both the
> > > + * .atomic_enable() and .atomic_flush() handlers.
> > > + */
> > > + if (rcrtc->initialized)
> > > + return 0;
> > > +
> > > + ret = clk_prepare_enable(rcrtc->rzg2l_clocks.aclk);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + ret = clk_prepare_enable(rcrtc->rzg2l_clocks.pclk);
> > > + if (ret < 0)
> > > + goto error_bus_clock;
> > > +
> > > + ret = reset_control_deassert(rcrtc->rstc);
> > > + if (ret < 0)
> > > + goto error_peri_clock;
> > > +
> > > + rzg2l_du_crtc_setup(rcrtc);
> > > + rcrtc->initialized = true;
> > > +
> > > + return 0;
> > > +
> > > +error_peri_clock:
> > > + clk_disable_unprepare(rcrtc->rzg2l_clocks.pclk);
> > > +error_bus_clock:
> > > + clk_disable_unprepare(rcrtc->rzg2l_clocks.aclk);
> > > + return ret;
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rcrtc)
> > > +{
> > > + clk_disable_unprepare(rcrtc->rzg2l_clocks.dclk);
> > > + reset_control_assert(rcrtc->rstc);
> > > + clk_disable_unprepare(rcrtc->rzg2l_clocks.pclk);
> > > + clk_disable_unprepare(rcrtc->rzg2l_clocks.aclk);
> > > +
> > > + rcrtc->initialized = false;
> > > +}
> > > +
> > > +static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool
> > start)
> > > +{
> > > + struct rzg2l_du_device *rcdu = rcrtc->dev;
> > > +
> > > + writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0);
> >
> > Why not using rzg2l_du_write() ?
>
> Missed it. Will change.
>
> >
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc)
> > > +{
> > > + rzg2l_du_start_stop(rcrtc, true);
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_stop(struct rzg2l_du_crtc *rcrtc)
> > > +{
> > > + struct drm_crtc *crtc = &rcrtc->crtc;
> > > +
> > > + /*
> > > + * Disable vertical blanking interrupt reporting. We first need to
> > wait
> > > + * for page flip completion before stopping the CRTC as userspace
> > > + * expects page flips to eventually complete.
> > > + */
> > > + rzg2l_du_crtc_wait_page_flip(rcrtc);
> > > + drm_crtc_vblank_off(crtc);
> > > +
> > > + /* Disable the VSP compositor. */
> > > + rzg2l_du_vsp_disable(rcrtc);
> > > +
> > > + rzg2l_du_start_stop(rcrtc, false);
> > > +}
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * CRTC Functions
> > > + */
> > > +
> > > +static void rzg2l_du_crtc_atomic_enable(struct drm_crtc *crtc,
> > > + struct drm_atomic_state *state)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
> > > +
> > > + rzg2l_du_crtc_get(rcrtc);
> > > +
> > > + rzg2l_du_crtc_start(rcrtc);
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_atomic_disable(struct drm_crtc *crtc,
> > > + struct drm_atomic_state *state)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
> > > +
> > > + rzg2l_du_crtc_stop(rcrtc);
> > > + rzg2l_du_crtc_put(rcrtc);
> > > +
> > > + spin_lock_irq(&crtc->dev->event_lock);
> > > + if (crtc->state->event) {
> > > + drm_crtc_send_vblank_event(crtc, crtc->state->event);
> > > + crtc->state->event = NULL;
> > > + }
> > > + spin_unlock_irq(&crtc->dev->event_lock);
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_atomic_flush(struct drm_crtc *crtc,
> > > + struct drm_atomic_state *state)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
> > > + struct drm_device *dev = rcrtc->crtc.dev;
> > > + unsigned long flags;
> > > +
> > > + WARN_ON(!crtc->state->enable);
> > > +
> > > + /*
> > > + * If a mode set is in progress we can be called with the CRTC
> > disabled.
> > > + * We thus need to first get and setup the CRTC in order to
> > configure
> > > + * planes. We must *not* put the CRTC, as it must be kept awake
> > until
> > > + * the .atomic_enable() call that will follow. The get operation in
> > > + * .atomic_enable() will in that case be a no-op, and the CRTC will
> > be
> > > + * put later in .atomic_disable().
> > > + */
> > > + rzg2l_du_crtc_get(rcrtc);
> > > +
> > > + if (crtc->state->event) {
> > > + WARN_ON(drm_crtc_vblank_get(crtc) != 0);
> > > +
> > > + spin_lock_irqsave(&dev->event_lock, flags);
> > > + rcrtc->event = crtc->state->event;
> > > + crtc->state->event = NULL;
> > > + spin_unlock_irqrestore(&dev->event_lock, flags);
> > > + }
> > > +
> > > + rzg2l_du_vsp_atomic_flush(rcrtc);
> > > +}
> > > +
> > > +static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
> > > + .atomic_flush = rzg2l_du_crtc_atomic_flush,
> > > + .atomic_enable = rzg2l_du_crtc_atomic_enable,
> > > + .atomic_disable = rzg2l_du_crtc_atomic_disable,
> > > +};
> > > +
> > > +static void rzg2l_du_crtc_crc_init(struct rzg2l_du_crtc *rcrtc)
> > > +{
> > > + const char **sources;
> > > + unsigned int count;
> > > + int i = -1;
> > > +
> > > + /* Reserve 1 for "auto" source. */
> > > + count = rcrtc->vsp->num_planes + 1;
> >
> > What's the "auto" source ?
>
> Good catch. there is no CRC available on VSP, I will drop all CRC stuff.
>
> >
> > > +
> > > + sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
> > > + if (!sources)
> > > + return;
> > > +
> > > + sources[0] = kstrdup("auto", GFP_KERNEL);
> > > + if (!sources[0])
> > > + goto error;
> >
> > Am I wrong or if you jump to error here, 'i == -1' and you won't free
> > sources[0] and neither sources ?
>
> I am planning to drop all crc api's from this file
> as VSP doesn't support CRC compared to R-Car.
>
> >
> > > +
> > > + for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
> > > + struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
> > > + char name[16];
> > > +
> > > + sprintf(name, "plane%u", plane->base.id);
> > > + sources[i + 1] = kstrdup(name, GFP_KERNEL);
> > > + if (!sources[i + 1])
> > > + goto error;
> > > + }
> > > +
> > > + rcrtc->sources = sources;
> > > + rcrtc->sources_count = count;
> > > + return;
> > > +
> > > +error:
> > > + while (i >= 0) {
> > > + kfree(sources[i]);
> > > + i--;
> > > + }
> > > + kfree(sources);
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_crc_cleanup(struct rzg2l_du_crtc *rcrtc)
> > > +{
> > > + unsigned int i;
> > > +
> > > + if (!rcrtc->sources)
> > > + return;
> > > +
> > > + for (i = 0; i < rcrtc->sources_count; i++)
> > > + kfree(rcrtc->sources[i]);
> > > + kfree(rcrtc->sources);
> > > +
> > > + rcrtc->sources = NULL;
> > > + rcrtc->sources_count = 0;
> > > +}
> > > +
> > > +static struct drm_crtc_state *
> > > +rzg2l_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
> > > +{
> > > + struct rzg2l_du_crtc_state *state;
> > > + struct rzg2l_du_crtc_state *copy;
> > > +
> > > + if (WARN_ON(!crtc->state))
> > > + return NULL;
> > > +
> > > + state = to_rzg2l_crtc_state(crtc->state);
> > > + copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
> > > + if (!copy)
> > > + return NULL;
> > > +
> > > + __drm_atomic_helper_crtc_duplicate_state(crtc, ©->state);
> > > +
> > > + return ©->state;
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
> > > + struct drm_crtc_state *state)
> > > +{
> > > + __drm_atomic_helper_crtc_destroy_state(state);
> > > + kfree(to_rzg2l_crtc_state(state));
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_cleanup(struct drm_crtc *crtc)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
> > > +
> > > + rzg2l_du_crtc_crc_cleanup(rcrtc);
> > > +
> > > + return drm_crtc_cleanup(crtc);
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_reset(struct drm_crtc *crtc)
> > > +{
> > > + struct rzg2l_du_crtc_state *state;
> > > +
> > > + if (crtc->state) {
> > > + rzg2l_du_crtc_atomic_destroy_state(crtc, crtc->state);
> > > + crtc->state = NULL;
> > > + }
> > > +
> > > + state = kzalloc(sizeof(*state), GFP_KERNEL);
> > > + if (!state)
> > > + return;
> > > +
> > > + state->crc.source = VSP1_DU_CRC_NONE;
> > > +
> > > + __drm_atomic_helper_crtc_reset(crtc, &state->state);
> > > +}
> > > +
> > > +static int rzg2l_du_crtc_enable_vblank(struct drm_crtc *crtc)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
> > > +
> > > + rcrtc->vblank_enable = true;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void rzg2l_du_crtc_disable_vblank(struct drm_crtc *crtc)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
> > > +
> > > + rcrtc->vblank_enable = false;
> > > +}
> > > +
> > > +static int rzg2l_du_crtc_parse_crc_source(struct rzg2l_du_crtc *rcrtc,
> > > + const char *source_name,
> > > + enum vsp1_du_crc_source *source)
> > > +{
> > > + unsigned int index;
> > > + int ret;
> > > +
> > > + /*
> > > + * Parse the source name. Supported values are "plane%u" to compute
> > the
> > > + * CRC on an input plane (%u is the plane ID), and "auto" to compute
> > the
> > > + * CRC on the composer (VSP) output.
> > > + */
> > > +
> > > + if (!source_name) {
> > > + *source = VSP1_DU_CRC_NONE;
> > > + return 0;
> > > + } else if (!strcmp(source_name, "auto")) {
> > > + *source = VSP1_DU_CRC_OUTPUT;
> > > + return 0;
> > > + } else if (strstarts(source_name, "plane")) {
> > > + unsigned int i;
> > > +
> > > + *source = VSP1_DU_CRC_PLANE;
> > > +
> > > + ret = kstrtouint(source_name + strlen("plane"), 10, &index);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
> > > + if (index == rcrtc->vsp->planes[i].plane.base.id)
> > > + return i;
> > > + }
> > > + }
> > > +
> >
> > Would like to check with Laurent what CRC calculation module this
> > feature supports, as I see CRC being performed on R-Car by a compnent
> > I don't see present on RZ G2L
>
> I am planning to drop CRC as it is not supported on RZ/G2L.
>
> >
> > > + return -EINVAL;
> > > +}
> > > +
> > > +static int rzg2l_du_crtc_verify_crc_source(struct drm_crtc *crtc,
> > > + const char *source_name,
> > > + size_t *values_cnt)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
> > > + enum vsp1_du_crc_source source;
> > > +
> > > + if (rzg2l_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0)
> > {
> > > + DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + *values_cnt = 1;
> > > + return 0;
> > > +}
> > > +
> > > +static const char *const *
> > > +rzg2l_du_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
> > > +
> > > + *count = rcrtc->sources_count;
> > > + return rcrtc->sources;
> > > +}
> > > +
> > > +static int rzg2l_du_crtc_set_crc_source(struct drm_crtc *crtc,
> > > + const char *source_name)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
> > > + struct drm_modeset_acquire_ctx ctx;
> > > + struct drm_crtc_state *crtc_state;
> > > + struct drm_atomic_state *state;
> > > + enum vsp1_du_crc_source source;
> > > + unsigned int index;
> > > + int ret;
> > > +
> > > + ret = rzg2l_du_crtc_parse_crc_source(rcrtc, source_name, &source);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + index = ret;
> > > +
> > > + /* Perform an atomic commit to set the CRC source. */
> > > + drm_modeset_acquire_init(&ctx, 0);
> > > +
> > > + state = drm_atomic_state_alloc(crtc->dev);
> > > + if (!state) {
> > > + ret = -ENOMEM;
> > > + goto unlock;
> > > + }
> > > +
> > > + state->acquire_ctx = &ctx;
> > > +
> > > +retry:
> > > + crtc_state = drm_atomic_get_crtc_state(state, crtc);
> > > + if (!IS_ERR(crtc_state)) {
> > > + struct rzg2l_du_crtc_state *rcrtc_state;
> > > +
> > > + rcrtc_state = to_rzg2l_crtc_state(crtc_state);
> > > + rcrtc_state->crc.source = source;
> > > + rcrtc_state->crc.index = index;
> > > +
> > > + ret = drm_atomic_commit(state);
> > > + } else {
> > > + ret = PTR_ERR(crtc_state);
> > > + }
> > > +
> > > + if (ret == -EDEADLK) {
> > > + drm_atomic_state_clear(state);
> > > + drm_modeset_backoff(&ctx);
> > > + goto retry;
> > > + }
> > > +
> > > + drm_atomic_state_put(state);
> > > +
> > > +unlock:
> > > + drm_modeset_drop_locks(&ctx);
> > > + drm_modeset_acquire_fini(&ctx);
> > > +
> > > + return ret;
> > > +}
> > > +
> > > +static const struct drm_crtc_funcs crtc_funcs_rz = {
> > > + .reset = rzg2l_du_crtc_reset,
> > > + .destroy = rzg2l_du_crtc_cleanup,
> > > + .set_config = drm_atomic_helper_set_config,
> > > + .page_flip = drm_atomic_helper_page_flip,
> > > + .atomic_duplicate_state = rzg2l_du_crtc_atomic_duplicate_state,
> > > + .atomic_destroy_state = rzg2l_du_crtc_atomic_destroy_state,
> > > + .enable_vblank = rzg2l_du_crtc_enable_vblank,
> > > + .disable_vblank = rzg2l_du_crtc_disable_vblank,
> > > + .set_crc_source = rzg2l_du_crtc_set_crc_source,
> > > + .verify_crc_source = rzg2l_du_crtc_verify_crc_source,
> > > + .get_crc_sources = rzg2l_du_crtc_get_crc_sources,
> > > +};
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Initialization
> > > + */
> > > +
> > > +int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu)
> > > +{
> > > + struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[0];
> > > + struct drm_crtc *crtc = &rcrtc->crtc;
> > > + struct drm_plane *primary;
> > > + int ret;
> > > +
> > > + rcrtc->rstc = devm_reset_control_get_shared(rcdu->dev, NULL);
> > > + if (IS_ERR(rcrtc->rstc)) {
> > > + dev_err(rcdu->dev, "can't get cpg reset\n");
> > > + return PTR_ERR(rcrtc->rstc);
> > > + }
> > > +
> > > + rcrtc->rzg2l_clocks.aclk = devm_clk_get(rcdu->dev, "aclk");
> > > + if (IS_ERR(rcrtc->rzg2l_clocks.aclk)) {
> > > + dev_err(rcdu->dev, "no axi clock for DU\n");
> > > + return PTR_ERR(rcrtc->rzg2l_clocks.aclk);
> > > + }
> > > +
> > > + rcrtc->rzg2l_clocks.pclk = devm_clk_get(rcdu->dev, "pclk");
> > > + if (IS_ERR(rcrtc->rzg2l_clocks.pclk)) {
> > > + dev_err(rcdu->dev, "no peripheral clock for DU\n");
> > > + return PTR_ERR(rcrtc->rzg2l_clocks.pclk);
> > > + }
> > > +
> > > + rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk");
> > > + if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) {
> > > + dev_err(rcdu->dev, "no video clock for DU\n");
> > > + return PTR_ERR(rcrtc->rzg2l_clocks.dclk);
> > > + }
> > > +
> > > + init_waitqueue_head(&rcrtc->flip_wait);
> > > + rcrtc->dev = rcdu;
> > > +
> > > + primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
> > > +
> > > + ret = drm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL,
> > > + &crtc_funcs_rz, NULL);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + drm_crtc_helper_add(crtc, &crtc_helper_funcs);
> > > +
> > > + rzg2l_du_crtc_crc_init(rcrtc);
> > > +
> > > + return 0;
> > > +}
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h
> > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h
> > > new file mode 100644
> > > index 000000000000..c067e07b5a95
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h
> > > @@ -0,0 +1,92 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * RZ/G2L Display Unit CRTCs
> > > + *
> > > + * Copyright (C) 2023 Renesas Electronics Corporation
> > > + *
> > > + * Based on rcar_du_crtc.h
> > > + */
> > > +
> > > +#ifndef __RZG2L_DU_CRTC_H__
> > > +#define __RZG2L_DU_CRTC_H__
> > > +
> > > +#include <linux/container_of.h>
> > > +#include <linux/mutex.h>
> > > +#include <linux/spinlock.h>
> > > +#include <linux/wait.h>
> > > +
> > > +#include <drm/drm_crtc.h>
> > > +#include <drm/drm_writeback.h>
> > > +
> > > +#include <media/vsp1.h>
> > > +
> > > +struct clk;
> > > +struct reset_control;
> > > +struct rzg2l_du_vsp;
> > > +struct rzg2l_du_format_info;
> > > +
> > > +/**
> > > + * struct rzg2l_du_crtc - the CRTC, representing a DU superposition
> > processor
> > > + * @crtc: base DRM CRTC
> > > + * @dev: the DU device
> > > + * @initialized: whether the CRTC has been initialized and clocks
> > enabled
> > > + * @vblank_enable: whether vblank events are enabled on this CRTC
> > > + * @event: event to post when the pending page flip completes
> > > + * @flip_wait: wait queue used to signal page flip completion
> > > + * @vsp: VSP feeding video to this CRTC
> > > + * @vsp_pipe: index of the VSP pipeline feeding video to this CRTC
> > > + * @rstc: reset controller
> > > + * @rzg2l_clocks: the bus, main and video clock
> > > + */
> > > +struct rzg2l_du_crtc {
> > > + struct drm_crtc crtc;
> > > +
> > > + struct rzg2l_du_device *dev;
> > > + bool initialized;
> > > +
> > > + bool vblank_enable;
> > > + struct drm_pending_vblank_event *event;
> > > + wait_queue_head_t flip_wait;
> > > +
> > > + struct rzg2l_du_vsp *vsp;
> > > + unsigned int vsp_pipe;
> > > +
> > > + const char *const *sources;
> > > + unsigned int sources_count;
> > > +
> > > + struct reset_control *rstc;
> > > + struct {
> > > + struct clk *aclk;
> > > + struct clk *pclk;
> > > + struct clk *dclk;
> > > + } rzg2l_clocks;
> > > +};
> > > +
> > > +static inline struct rzg2l_du_crtc *to_rzg2l_crtc(struct drm_crtc *c)
> > > +{
> > > + return container_of(c, struct rzg2l_du_crtc, crtc);
> > > +}
> > > +
> > > +/**
> > > + * struct rzg2l_du_crtc_state - Driver-specific CRTC state
> > > + * @state: base DRM CRTC state
> > > + * @crc: CRC computation configuration
> > > + * @outputs: bitmask of the outputs (enum rzg2l_du_output) driven by
> > this CRTC
> > > + */
> > > +struct rzg2l_du_crtc_state {
> > > + struct drm_crtc_state state;
> > > +
> > > + struct vsp1_du_crc_config crc;
> > > + unsigned int outputs;
> > > +};
> > > +
> > > +static inline struct rzg2l_du_crtc_state *to_rzg2l_crtc_state(struct
> > drm_crtc_state *s)
> > > +{
> > > + return container_of(s, struct rzg2l_du_crtc_state, state);
> > > +}
> > > +
> > > +int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu);
> > > +
> > > +void rzg2l_du_crtc_finish_page_flip(struct rzg2l_du_crtc *rcrtc);
> > > +
> > > +#endif /* __RZG2L_DU_CRTC_H__ */
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > new file mode 100644
> > > index 000000000000..6aee96b23570
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > @@ -0,0 +1,180 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * RZ/G2L Display Unit DRM driver
> > > + *
> > > + * Copyright (C) 2023 Renesas Electronics Corporation
> > > + *
> > > + * Based on rcar_du_drv.c
> > > + */
> > > +
> > > +#include <linux/dma-mapping.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_device.h>
> > > +#include <linux/platform_device.h>
> > > +
> > > +#include <drm/drm_atomic_helper.h>
> > > +#include <drm/drm_drv.h>
> > > +#include <drm/drm_fbdev_generic.h>
> > > +#include <drm/drm_gem_dma_helper.h>
> > > +#include <drm/drm_probe_helper.h>
> > > +
> > > +#include "rzg2l_du_drv.h"
> > > +#include "rzg2l_du_kms.h"
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Device Information
> > > + */
> > > +
> > > +static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
> > > + .channels_mask = BIT(0),
> > > + .routes = {
> > > + [RZG2L_DU_OUTPUT_DSI0] = {
> > > + .possible_crtcs = BIT(0),
> > > + .port = 0,
> > > + },
> > > + [RZG2L_DU_OUTPUT_DPAD0] = {
> > > + .possible_crtcs = BIT(0),
> > > + .port = 1,
> > > + }
> > > + }
> > > +};
> > > +
> > > +static const struct of_device_id rzg2l_du_of_table[] = {
> > > + { .compatible = "renesas,r9a07g044-du", .data =
> > &rzg2l_du_r9a07g044_info },
> > > + { /* sentinel */ }
> > > +};
> > > +
> > > +MODULE_DEVICE_TABLE(of, rzg2l_du_of_table);
> > > +
> > > +const char *rzg2l_du_output_name(enum rzg2l_du_output output)
> > > +{
> > > + static const char * const names[] = {
> > > + [RZG2L_DU_OUTPUT_DSI0] = "DSI0",
> > > + [RZG2L_DU_OUTPUT_DPAD0] = "DPAD0"
> > > + };
> > > +
> > > + if (output >= ARRAY_SIZE(names))
> > > + return "UNKNOWN";
> > > +
> > > + return names[output];
> > > +}
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * DRM operations
> > > + */
> > > +
> > > +DEFINE_DRM_GEM_DMA_FOPS(rzg2l_du_fops);
> > > +
> > > +static const struct drm_driver rzg2l_du_driver = {
> > > + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> > > + .dumb_create = rzg2l_du_dumb_create,
> > > + .gem_prime_import_sg_table = rzg2l_du_gem_prime_import_sg_table,
> > > + .fops = &rzg2l_du_fops,
> > > + .name = "rzg2l-du",
> > > + .desc = "Renesas RZ/G2L Display Unit",
> > > + .date = "20230410",
> > > + .major = 1,
> > > + .minor = 0,
> > > +};
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Platform driver
> > > + */
> > > +
> > > +static void rzg2l_du_remove(struct platform_device *pdev)
> > > +{
> > > + struct rzg2l_du_device *rcdu = platform_get_drvdata(pdev);
> > > + struct drm_device *ddev = &rcdu->ddev;
> > > +
> > > + drm_dev_unregister(ddev);
> > > + drm_atomic_helper_shutdown(ddev);
> > > +
> > > + drm_kms_helper_poll_fini(ddev);
> > > +}
> > > +
> > > +static void rzg2l_du_shutdown(struct platform_device *pdev)
> > > +{
> > > + struct rzg2l_du_device *rcdu = platform_get_drvdata(pdev);
> > > +
> > > + drm_atomic_helper_shutdown(&rcdu->ddev);
> > > +}
> > > +
> > > +static int rzg2l_du_probe(struct platform_device *pdev)
> > > +{
> > > + struct rzg2l_du_device *rcdu;
> > > + int ret;
> > > +
> > > + if (drm_firmware_drivers_only())
> > > + return -ENODEV;
> > > +
> > > + /* Allocate and initialize the RZ/G2L device structure. */
> > > + rcdu = devm_drm_dev_alloc(&pdev->dev, &rzg2l_du_driver,
> > > + struct rzg2l_du_device, ddev);
> > > + if (IS_ERR(rcdu))
> > > + return PTR_ERR(rcdu);
> > > +
> > > + rcdu->dev = &pdev->dev;
> > > + rcdu->info = of_device_get_match_data(rcdu->dev);
> > > +
> > > + platform_set_drvdata(pdev, rcdu);
> > > +
> > > + /* I/O resources */
> > > + rcdu->mmio = devm_platform_ioremap_resource(pdev, 0);
> > > + if (IS_ERR(rcdu->mmio))
> > > + return PTR_ERR(rcdu->mmio);
> > > +
> > > + /*
> > > + * When sourcing frames from a VSP the DU doesn't perform any memory
> > > + * access so set the DMA coherent mask to 40 bits to accept all
> > buffers.
> > > + */
> > > + ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
> > > + if (ret)
> > > + return ret;
> >
> > Does this apply to RZ G2L too ? (Maybe I don't fully get what the
> > implications are here)
>
> Will change it to 32-bit mask and remove the comment.
>
> >
> > > +
> > > + /* DRM/KMS objects */
> > > + ret = rzg2l_du_modeset_init(rcdu);
> > > + if (ret < 0) {
> > > + /*
> > > + * Don't use dev_err_probe(), as it would overwrite the probe
> > > + * deferral reason recorded in rzg2l_du_modeset_init().
> > > + */
> > > + if (ret != -EPROBE_DEFER)
> > > + dev_err(&pdev->dev,
> > > + "failed to initialize DRM/KMS (%d)\n", ret);
> > > + goto error;
> > > + }
> > > +
> > > + /*
> > > + * Register the DRM device with the core and the connectors with
> > > + * sysfs.
> > > + */
> > > + ret = drm_dev_register(&rcdu->ddev, 0);
> > > + if (ret)
> > > + goto error;
> > > +
> > > + drm_info(&rcdu->ddev, "Device %s probed\n", dev_name(&pdev->dev));
> > > +
> > > + drm_fbdev_generic_setup(&rcdu->ddev, 32);
> > > +
> > > + return 0;
> > > +
> > > +error:
> > > + drm_kms_helper_poll_fini(&rcdu->ddev);
> > > + return ret;
> > > +}
> > > +
> > > +static struct platform_driver rzg2l_du_platform_driver = {
> > > + .probe = rzg2l_du_probe,
> > > + .remove_new = rzg2l_du_remove,
> > > + .shutdown = rzg2l_du_shutdown,
> > > + .driver = {
> > > + .name = "rzg2l-du",
> > > + .of_match_table = rzg2l_du_of_table,
> > > + },
> > > +};
> > > +
> > > +module_platform_driver(rzg2l_du_platform_driver);
> > > +
> > > +MODULE_AUTHOR("Biju Das <biju.das.jz@xxxxxxxxxxxxxx>");
> > > +MODULE_DESCRIPTION("Renesas RZ/G2L Display Unit DRM Driver");
> > > +MODULE_LICENSE("GPL");
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > new file mode 100644
> > > index 000000000000..2a82c5beea0a
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > @@ -0,0 +1,84 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * RZ/G2L Display Unit DRM driver
> > > + *
> > > + * Copyright (C) 2023 Renesas Electronics Corporation
> > > + *
> > > + * Based on rcar_du_drv.h
> > > + */
> > > +
> > > +#ifndef __RZG2L_DU_DRV_H__
> > > +#define __RZG2L_DU_DRV_H__
> > > +
> > > +#include <linux/kernel.h>
> > > +
> > > +#include <drm/drm_device.h>
> > > +
> > > +#include "rzg2l_du_crtc.h"
> > > +#include "rzg2l_du_vsp.h"
> > > +
> > > +struct device;
> > > +struct drm_bridge;
> >
> > Not used apparently
>
> Will remove it.
>
> >
> > > +struct drm_property;
> > > +
> > > +enum rzg2l_du_output {
> > > + RZG2L_DU_OUTPUT_DSI0,
> > > + RZG2L_DU_OUTPUT_DPAD0,
> > > + RZG2L_DU_OUTPUT_MAX,
> > > +};
> > > +
> > > +/*
> > > + * struct rzg2l_du_output_routing - Output routing specification
> > > + * @possible_crtcs: bitmask of possible CRTCs for the output
> > > + * @port: device tree port number corresponding to this output route
> > > + *
> > > + * The DU has 2 possible outputs (DPAD0, DSI0). Output routing data
> > > + * specify the valid SoC outputs, which CRTCs can drive the output,
> and
> > the type
> > > + * of in-SoC encoder for the output.
> > > + */
> > > +struct rzg2l_du_output_routing {
> > > + unsigned int possible_crtcs;
> >
> > Does this make sense with a single CRTC ?
>
> Ok, Will change it to possible_outputs instead?
>
> >
> > > + unsigned int port;
> > > +};
> > > +
> > > +/*
> > > + * struct rzg2l_du_device_info - DU model-specific information
> > > + * @channels_mask: bit mask of available DU channels
> > > + * @routes: array of CRTC to output routes, indexed by output
> > (RZG2L_DU_OUTPUT_*)
> > > + */
> > > +struct rzg2l_du_device_info {
> > > + unsigned int channels_mask;
> > > + struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX];
> > > +};
> > > +
> > > +#define RZG2L_DU_MAX_CRTCS 1
> > > +#define RZG2L_DU_MAX_VSPS 1
> > > +#define RZG2L_DU_MAX_DSI 1
> > > +
> > > +struct rzg2l_du_device {
> > > + struct device *dev;
> > > + const struct rzg2l_du_device_info *info;
> > > +
> > > + void __iomem *mmio;
> > > +
> > > + struct drm_device ddev;
> > > +
> > > + struct rzg2l_du_crtc crtcs[RZG2L_DU_MAX_CRTCS];
> > > + unsigned int num_crtcs;
> > > +
> > > + struct rzg2l_du_vsp vsps[RZG2L_DU_MAX_VSPS];
> > > +
> > > + struct {
> > > + struct drm_property *colorkey;
> > > + } props;
> >
> > I don't see this propery being handled ?
> >
> > Does it make sense for RZ/G2L ?
>
> Will remove it, as only VSP support colour keying
> compared to colour keying support in plane in R-Car.
>
> >
> > > +
> >
> > Additional empty line ?
>
> Will remove it.
>
> >
> > > +};
> > > +
> > > +static inline struct rzg2l_du_device *to_rzg2l_du_device(struct
> > drm_device *dev)
> > > +{
> > > + return container_of(dev, struct rzg2l_du_device, ddev);
> > > +}
> > > +
> > > +const char *rzg2l_du_output_name(enum rzg2l_du_output output);
> > > +
> > > +#endif /* __RZG2L_DU_DRV_H__ */
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > new file mode 100644
> > > index 000000000000..f7ab5001d822
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > @@ -0,0 +1,109 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * RZ/G2L Display Unit Encoder
> > > + *
> > > + * Copyright (C) 2023 Renesas Electronics Corporation
> > > + *
> > > + * Based on rcar_du_encoder.c
> > > + */
> > > +
> > > +#include <linux/export.h>
> > > +#include <linux/of.h>
> > > +
> > > +#include <drm/drm_bridge.h>
> > > +#include <drm/drm_bridge_connector.h>
> > > +#include <drm/drm_panel.h>
> > > +
> > > +#include "rzg2l_du_drv.h"
> > > +#include "rzg2l_du_encoder.h"
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Encoder
> > > + */
> > > +
> > > +static unsigned int rzg2l_du_encoder_count_ports(struct device_node
> > *node)
> > > +{
> > > + struct device_node *ports;
> > > + struct device_node *port;
> > > + unsigned int num_ports = 0;
> > > +
> > > + ports = of_get_child_by_name(node, "ports");
> > > + if (!ports)
> > > + ports = of_node_get(node);
> > > +
> > > + for_each_child_of_node(ports, port) {
> > > + if (of_node_name_eq(port, "port"))
> > > + num_ports++;
> > > + }
> > > +
> > > + of_node_put(ports);
> > > +
> > > + return num_ports;
> > > +}
> > > +
> > > +static const struct drm_encoder_funcs rzg2l_du_encoder_funcs = {
> > > +};
> > > +
> > > +int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu,
> > > + enum rzg2l_du_output output,
> > > + struct device_node *enc_node)
> > > +{
> > > + struct rzg2l_du_encoder *renc;
> > > + struct drm_connector *connector;
> > > + struct drm_bridge *bridge;
> > > + int ret;
> > > +
> > > + /*
> > > + * Locate the DRM bridge from the DT node. For the DPAD outputs, if
> > the
> > > + * DT node has a single port, assume that it describes a panel and
> > > + * create a panel bridge.
> > > + */
> > > + if (output == RZG2L_DU_OUTPUT_DPAD0 &&
> > > + rzg2l_du_encoder_count_ports(enc_node) == 1) {
> > > + struct drm_panel *panel = of_drm_find_panel(enc_node);
> > > +
> > > + if (IS_ERR(panel))
> > > + return PTR_ERR(panel);
> > > +
> > > + bridge = devm_drm_panel_bridge_add_typed(rcdu->dev, panel,
> > > + DRM_MODE_CONNECTOR_DPI);
> > > + if (IS_ERR(bridge))
> > > + return PTR_ERR(bridge);
> > > + } else {
> > > + bridge = of_drm_find_bridge(enc_node);
> > > + if (!bridge)
> > > + return -EPROBE_DEFER;
> > > + }
> > > +
> > > + dev_dbg(rcdu->dev, "initializing encoder %pOF for output %s\n",
> > > + enc_node, rzg2l_du_output_name(output));
> > > +
> > > + renc = drmm_encoder_alloc(&rcdu->ddev, struct rzg2l_du_encoder,
> > base,
> > > + &rzg2l_du_encoder_funcs, DRM_MODE_ENCODER_NONE,
> > > + NULL);
> > > + if (IS_ERR(renc))
> > > + return PTR_ERR(renc);
> > > +
> > > + renc->output = output;
> > > +
> > > + /* Attach the bridge to the encoder. */
> > > + ret = drm_bridge_attach(&renc->base, bridge, NULL,
> > > + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> > > + if (ret) {
> > > + dev_err(rcdu->dev,
> > > + "failed to attach bridge %pOF for output %s (%d)\n",
> > > + bridge->of_node, rzg2l_du_output_name(output), ret);
> > > + return ret;
> > > + }
> > > +
> > > + /* Create the connector for the chain of bridges. */
> > > + connector = drm_bridge_connector_init(&rcdu->ddev, &renc->base);
> > > + if (IS_ERR(connector)) {
> > > + dev_err(rcdu->dev,
> > > + "failed to created connector for output %s (%ld)\n",
> > > + rzg2l_du_output_name(output), PTR_ERR(connector));
> > > + return PTR_ERR(connector);
> > > + }
> > > +
> > > + return drm_connector_attach_encoder(connector, &renc->base);
> > > +}
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h
> > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h
> > > new file mode 100644
> > > index 000000000000..3e430c1f6132
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h
> > > @@ -0,0 +1,32 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * RZ/G2L Display Unit Encoder
> > > + *
> > > + * Copyright (C) 2023 Renesas Electronics Corporation
> > > + *
> > > + * Based on rcar_du_encoder.h
> > > + */
> > > +
> > > +#ifndef __RZG2L_DU_ENCODER_H__
> > > +#define __RZG2L_DU_ENCODER_H__
> > > +
> > > +#include <drm/drm_encoder.h>
> > > +#include <linux/container_of.h>
> > > +
> > > +struct rzg2l_du_device;
> > > +
> > > +struct rzg2l_du_encoder {
> > > + struct drm_encoder base;
> > > + enum rzg2l_du_output output;
> > > +};
> > > +
> > > +static inline struct rzg2l_du_encoder *to_rzg2l_encoder(struct
> > drm_encoder *e)
> > > +{
> > > + return container_of(e, struct rzg2l_du_encoder, base);
> > > +}
> > > +
> > > +int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu,
> > > + enum rzg2l_du_output output,
> > > + struct device_node *enc_node);
> > > +
> > > +#endif /* __RZG2L_DU_ENCODER_H__ */
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
> > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
> > > new file mode 100644
> > > index 000000000000..24d8166a9fef
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
> > > @@ -0,0 +1,741 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * RZ/G2L Display Unit Mode Setting
> > > + *
> > > + * Copyright (C) 2023 Renesas Electronics Corporation
> > > + *
> > > + * Based on rcar_du_kms.c
> > > + */
> > > +
> > > +#include <drm/drm_atomic.h>
> > > +#include <drm/drm_atomic_helper.h>
> > > +#include <drm/drm_crtc.h>
> > > +#include <drm/drm_device.h>
> > > +#include <drm/drm_framebuffer.h>
> > > +#include <drm/drm_gem_dma_helper.h>
> > > +#include <drm/drm_gem_framebuffer_helper.h>
> > > +#include <drm/drm_managed.h>
> > > +#include <drm/drm_probe_helper.h>
> > > +#include <drm/drm_vblank.h>
> > > +
> > > +#include <linux/device.h>
> > > +#include <linux/of_graph.h>
> > > +#include <linux/of_platform.h>
> > > +
> > > +#include "rzg2l_du_crtc.h"
> > > +#include "rzg2l_du_drv.h"
> > > +#include "rzg2l_du_encoder.h"
> > > +#include "rzg2l_du_kms.h"
> > > +#include "rzg2l_du_vsp.h"
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Format helpers
> > > + */
> > > +
> > > +static const struct rzg2l_du_format_info rzg2l_du_format_infos[] = {
> > > + {
> > > + .fourcc = DRM_FORMAT_RGB565,
> > > + .v4l2 = V4L2_PIX_FMT_RGB565,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_ARGB1555,
> > > + .v4l2 = V4L2_PIX_FMT_ARGB555,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_XRGB1555,
> > > + .v4l2 = V4L2_PIX_FMT_XRGB555,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_XRGB8888,
> > > + .v4l2 = V4L2_PIX_FMT_XBGR32,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_ARGB8888,
> > > + .v4l2 = V4L2_PIX_FMT_ABGR32,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_UYVY,
> > > + .v4l2 = V4L2_PIX_FMT_UYVY,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_YUYV,
> > > + .v4l2 = V4L2_PIX_FMT_YUYV,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_NV12,
> > > + .v4l2 = V4L2_PIX_FMT_NV12M,
> > > + .bpp = 12,
> > > + .planes = 2,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_NV21,
> > > + .v4l2 = V4L2_PIX_FMT_NV21M,
> > > + .bpp = 12,
> > > + .planes = 2,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_NV16,
> > > + .v4l2 = V4L2_PIX_FMT_NV16M,
> > > + .bpp = 16,
> > > + .planes = 2,
> > > + .hsub = 2,
> > > + },
> > > + {
> > > + .fourcc = DRM_FORMAT_RGB332,
> > > + .v4l2 = V4L2_PIX_FMT_RGB332,
> > > + .bpp = 8,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_ARGB4444,
> > > + .v4l2 = V4L2_PIX_FMT_ARGB444,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_XRGB4444,
> > > + .v4l2 = V4L2_PIX_FMT_XRGB444,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_RGBA4444,
> > > + .v4l2 = V4L2_PIX_FMT_RGBA444,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_RGBX4444,
> > > + .v4l2 = V4L2_PIX_FMT_RGBX444,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_ABGR4444,
> > > + .v4l2 = V4L2_PIX_FMT_ABGR444,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_XBGR4444,
> > > + .v4l2 = V4L2_PIX_FMT_XBGR444,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_BGRA4444,
> > > + .v4l2 = V4L2_PIX_FMT_BGRA444,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_BGRX4444,
> > > + .v4l2 = V4L2_PIX_FMT_BGRX444,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_RGBA5551,
> > > + .v4l2 = V4L2_PIX_FMT_RGBA555,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_RGBX5551,
> > > + .v4l2 = V4L2_PIX_FMT_RGBX555,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_ABGR1555,
> > > + .v4l2 = V4L2_PIX_FMT_ABGR555,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_XBGR1555,
> > > + .v4l2 = V4L2_PIX_FMT_XBGR555,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_BGRA5551,
> > > + .v4l2 = V4L2_PIX_FMT_BGRA555,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_BGRX5551,
> > > + .v4l2 = V4L2_PIX_FMT_BGRX555,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_BGR888,
> > > + .v4l2 = V4L2_PIX_FMT_RGB24,
> > > + .bpp = 24,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_RGB888,
> > > + .v4l2 = V4L2_PIX_FMT_BGR24,
> > > + .bpp = 24,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_RGBA8888,
> > > + .v4l2 = V4L2_PIX_FMT_BGRA32,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_RGBX8888,
> > > + .v4l2 = V4L2_PIX_FMT_BGRX32,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_ABGR8888,
> > > + .v4l2 = V4L2_PIX_FMT_RGBA32,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_XBGR8888,
> > > + .v4l2 = V4L2_PIX_FMT_RGBX32,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_BGRA8888,
> > > + .v4l2 = V4L2_PIX_FMT_ARGB32,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_BGRX8888,
> > > + .v4l2 = V4L2_PIX_FMT_XRGB32,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_RGBX1010102,
> > > + .v4l2 = V4L2_PIX_FMT_RGBX1010102,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_RGBA1010102,
> > > + .v4l2 = V4L2_PIX_FMT_RGBA1010102,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_ARGB2101010,
> > > + .v4l2 = V4L2_PIX_FMT_ARGB2101010,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_YVYU,
> > > + .v4l2 = V4L2_PIX_FMT_YVYU,
> > > + .bpp = 16,
> > > + .planes = 1,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_NV61,
> > > + .v4l2 = V4L2_PIX_FMT_NV61M,
> > > + .bpp = 16,
> > > + .planes = 2,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_YUV420,
> > > + .v4l2 = V4L2_PIX_FMT_YUV420M,
> > > + .bpp = 12,
> > > + .planes = 3,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_YVU420,
> > > + .v4l2 = V4L2_PIX_FMT_YVU420M,
> > > + .bpp = 12,
> > > + .planes = 3,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_YUV422,
> > > + .v4l2 = V4L2_PIX_FMT_YUV422M,
> > > + .bpp = 16,
> > > + .planes = 3,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_YVU422,
> > > + .v4l2 = V4L2_PIX_FMT_YVU422M,
> > > + .bpp = 16,
> > > + .planes = 3,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_YUV444,
> > > + .v4l2 = V4L2_PIX_FMT_YUV444M,
> > > + .bpp = 24,
> > > + .planes = 3,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_YVU444,
> > > + .v4l2 = V4L2_PIX_FMT_YVU444M,
> > > + .bpp = 24,
> > > + .planes = 3,
> > > + .hsub = 1,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_Y210,
> > > + .v4l2 = V4L2_PIX_FMT_Y210,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 2,
> > > + }, {
> > > + .fourcc = DRM_FORMAT_Y212,
> > > + .v4l2 = V4L2_PIX_FMT_Y212,
> > > + .bpp = 32,
> > > + .planes = 1,
> > > + .hsub = 2,
> > > + },
> > > +};
> >
> > I see listed as supported formats in the DU features list
> >
> > Input data format (from VSPD): RGB888, RGB666 (not supports dithering of
> > RGB565)
> > − Output data format: same as Input data format
> >
> > Am I missing something ?
>
> If you see the pipeline below, the Image buffer is read by RPF and finally
> rendered to DU as the VSP is the compositor.
>
> Imagebuffer (YUV) --> RPF(YUV)-->WPF(YUV)-->LIF(RGB)-->DU(RGB)
>
> I have tested the following modes with modetest utility and
> Seemed to work fine.
>
> 1920x1080@AR12
> 1920x1080@XR12
> 1920x1080@AR15
> 1920x1080@XR15
> 1920x1080@RG16
> 1920x1080@BG24
> 1920x1080@RG24
> 1920x1080@BA24
> 1920x1080@BX24
> 1920x1080@AR24
> 1920x1080@XR24
> 1920x1080@UYVY
> 1920x1080@YUYV
> 1920x1080@YVYU
> 1920x1080@NV12
> 1920x1080@NV21
> 1920x1080@NV16
> 1920x1080@NV61
>
> 1280x1024@AR12
> 1280x1024@XR12
> 1280x1024@AR15
> 1280x1024@XR15
> 1280x1024@RG16
> 1280x1024@BG24
> 1280x1024@RG24
> 1280x1024@BA24
> 1280x1024@BX24
> 1280x1024@AR24
> 1280x1024@XR24
> 1280x1024@UYVY
> 1280x1024@YUYV
> 1280x1024@YVYU
> 1280x1024@NV12
> 1280x1024@NV21
> 1280x1024@NV16
> 1280x1024@NV61
>
> 1152x864@AR12
> 1152x864@XR12
> 1152x864@AR15
> 1152x864@XR15
> 1152x864@RG16
> 1152x864@BG24
> 1152x864@RG24
> 1152x864@BA24
> 1152x864@BX24
> 1152x864@AR24
> 1152x864@XR24
> 1152x864@UYVY
> 1152x864@YUYV
> 1152x864@YVYU
> 1152x864@NV12
> 1152x864@NV21
> 1152x864@NV16
> 1152x864@NV61
>
> 1280x720@AR12
> 1280x720@XR12
> 1280x720@AR15
> 1280x720@XR15
> 1280x720@RG16
> 1280x720@BG24
> 1280x720@RG24
> 1280x720@BA24
> 1280x720@BX24
> 1280x720@AR24
> 1280x720@XR24
> 1280x720@UYVY
> 1280x720@YUYV
> 1280x720@YVYU
> 1280x720@NV12
> 1280x720@NV21
> 1280x720@NV16
> 1280x720@NV61
>
> 1024x768@AR12
> 1024x768@XR12
> 1024x768@AR15
> 1024x768@XR15
> 1024x768@RG16
> 1024x768@BG24
> 1024x768@RG24
> 1024x768@BA24
> 1024x768@BX24
> 1024x768@AR24
> 1024x768@XR24
> 1024x768@UYVY
> 1024x768@YUYV
> 1024x768@YVYU
> 1024x768@NV12
> 1024x768@NV21
> 1024x768@NV16
> 1024x768@NV61
>
> 832x624@AR12
> 832x624@XR12
> 832x624@AR15
> 832x624@XR15
> 832x624@RG16
> 832x624@BG24
> 832x624@RG24
> 832x624@BA24
> 832x624@BX24
> 832x624@AR24
> 832x624@XR24
> 832x624@UYVY
> 832x624@YUYV
> 832x624@YVYU
> 832x624@NV12
> 832x624@NV21
> 832x624@NV16
> 832x624@NV61
>
> 800x600@AR12
> 800x600@XR12
> 800x600@AR15
> 800x600@XR15
> 800x600@RG16
> 800x600@BG24
> 800x600@RG24
> 800x600@BA24
> 800x600@BX24
> 800x600@AR24
> 800x600@XR24
> 800x600@UYVY
> 800x600@YUYV
> 800x600@YVYU
> 800x600@NV12
> 800x600@NV21
> 800x600@NV16
> 800x600@NV61
>
> 720x576@AR12
> 720x576@XR12
> 720x576@AR15
> 720x576@XR15
> 720x576@RG16
> 720x576@BG24
> 720x576@RG24
> 720x576@BA24
> 720x576@BX24
> 720x576@AR24
> 720x576@XR24
> 720x576@UYVY
> 720x576@YUYV
> 720x576@YVYU
> 720x576@NV12
> 720x576@NV21
> 720x576@NV16
> 720x576@NV61
>
> 720x480@AR12
> 720x480@XR12
> 720x480@AR15
> 720x480@XR15
> 720x480@RG16
> 720x480@BG24
> 720x480@RG24
> 720x480@BA24
> 720x480@BX24
> 720x480@AR24
> 720x480@XR24
> 720x480@UYVY
> 720x480@YUYV
> 720x480@YVYU
> 720x480@NV12
> 720x480@NV21
> 720x480@NV16
> 720x480@NV61
>
> 640x480@AR12
> 640x480@XR12
> 640x480@AR15
> 640x480@XR15
> 640x480@RG16
> 640x480@BG24
> 640x480@RG24
> 640x480@BA24
> 640x480@BX24
> 640x480@AR24
> 640x480@XR24
> 640x480@UYVY
> 640x480@YUYV
> 640x480@YVYU
> 640x480@NV12
> 640x480@NV21
> 640x480@NV16
> 640x480@NV61
>
> 720x400@AR12
> 720x400@XR12
> 720x400@AR15
> 720x400@XR15
> 720x400@RG16
> 720x400@BG24
> 720x400@RG24
> 720x400@BA24
> 720x400@BX24
> 720x400@AR24
> 720x400@XR24
> 720x400@UYVY
> 720x400@YUYV
> 720x400@YVYU
> 720x400@NV12
> 720x400@NV21
> 720x400@NV16
> 720x400@NV61
>
> >
> > > +
> > > +const struct rzg2l_du_format_info *rzg2l_du_format_info(u32 fourcc)
> > > +{
> > > + unsigned int i;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(rzg2l_du_format_infos); ++i) {
> > > + if (rzg2l_du_format_infos[i].fourcc == fourcc)
> > > + return &rzg2l_du_format_infos[i];
> > > + }
> > > +
> > > + return NULL;
> > > +}
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Frame buffer
> > > + */
> > > +
> > > +static const struct drm_gem_object_funcs rzg2l_du_gem_funcs = {
> > > + .free = drm_gem_dma_object_free,
> > > + .print_info = drm_gem_dma_object_print_info,
> > > + .get_sg_table = drm_gem_dma_object_get_sg_table,
> > > + .vmap = drm_gem_dma_object_vmap,
> > > + .mmap = drm_gem_dma_object_mmap,
> > > + .vm_ops = &drm_gem_dma_vm_ops,
> > > +};
> > > +
> > > +struct drm_gem_object *
> > > +rzg2l_du_gem_prime_import_sg_table(struct drm_device *dev,
> > > + struct dma_buf_attachment *attach,
> > > + struct sg_table *sgt)
> > > +{
> > > + struct drm_gem_dma_object *dma_obj;
> > > + struct drm_gem_object *gem_obj;
> > > + int ret;
> > > +
> > > + /* Create a DMA GEM buffer. */
> > > + dma_obj = kzalloc(sizeof(*dma_obj), GFP_KERNEL);
> > > + if (!dma_obj)
> > > + return ERR_PTR(-ENOMEM);
> > > +
> > > + gem_obj = &dma_obj->base;
> > > + gem_obj->funcs = &rzg2l_du_gem_funcs;
> > > +
> > > + drm_gem_private_object_init(dev, gem_obj, attach->dmabuf->size);
> > > + dma_obj->map_noncoherent = false;
> > > +
> > > + ret = drm_gem_create_mmap_offset(gem_obj);
> > > + if (ret) {
> > > + drm_gem_object_release(gem_obj);
> > > + kfree(dma_obj);
> > > + return ERR_PTR(ret);
> > > + }
> > > +
> > > + dma_obj->dma_addr = 0;
> > > + dma_obj->sgt = sgt;
> > > +
> > > + return gem_obj;
> > > +}
> > > +
> > > +int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device
> *dev,
> > > + struct drm_mode_create_dumb *args)
> > > +{
> > > + unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
> > > + unsigned int align = 16 * args->bpp / 8;
> > > +
> > > + args->pitch = roundup(min_pitch, align);
> > > +
> > > + return drm_gem_dma_dumb_create_internal(file, dev, args);
> > > +}
> > > +
> > > +static struct drm_framebuffer *
> > > +rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
> > > + const struct drm_mode_fb_cmd2 *mode_cmd)
> > > +{
> > > + const struct rzg2l_du_format_info *format;
> > > + unsigned int chroma_pitch;
> > > + unsigned int max_pitch;
> > > + unsigned int align;
> > > + unsigned int i;
> > > +
> > > + format = rzg2l_du_format_info(mode_cmd->pixel_format);
> > > + if (!format) {
> > > + dev_dbg(dev->dev, "unsupported pixel format %p4cc\n",
> > > + &mode_cmd->pixel_format);
> > > + return ERR_PTR(-EINVAL);
> > > + }
> > > +
> > > + /*
> > > + * On Gen3 the memory interface is handled by the VSP that limits
> > the
> > > + * pitch to 65535 bytes and has no alignment constraint.
> > > + */
> > > + max_pitch = 65535;
> > > + align = 1;
> >
> > Does this apply to RZ G2L ?
>
> I think so as it is the same as V3M. I will change the comment to
> Gen3->RZ/G2L to make it consistent.
>
> >
> > > +
> > > + if (mode_cmd->pitches[0] & (align - 1) ||
> > > + mode_cmd->pitches[0] > max_pitch) {
> > > + dev_dbg(dev->dev, "invalid pitch value %u\n",
> > > + mode_cmd->pitches[0]);
> > > + return ERR_PTR(-EINVAL);
> > > + }
> > > +
> > > + /*
> > > + * Calculate the chroma plane(s) pitch using the horizontal
> > subsampling
> > > + * factor. For semi-planar formats, the U and V planes are combined,
> > the
> > > + * pitch must thus be doubled.
> > > + */
> > > + chroma_pitch = mode_cmd->pitches[0] / format->hsub;
> > > + if (format->planes == 2)
> > > + chroma_pitch *= 2;
> >
> > Only makes sense if the interface actually supports YUV
>
> As VSP is the compositor and it supports YUV, I think it is correct.
> Please see the below pipeline.
>
> Imagebuffer (YUV) --> RPF(YUV)-->WPF(YUV)-->LIF(RGB)-->DU(RGB)
>
> Currently I have tested YUV formats using modetest.
>
> >
> > > +
> > > + for (i = 1; i < format->planes; ++i) {
> > > + if (mode_cmd->pitches[i] != chroma_pitch) {
> > > + dev_dbg(dev->dev,
> > > + "luma and chroma pitches are not compatible\n");
> > > + return ERR_PTR(-EINVAL);
> > > + }
> > > + }
> > > +
> > > + return drm_gem_fb_create(dev, file_priv, mode_cmd);
> > > +}
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Atomic Check and Update
> > > + */
> > > +
> > > +static void rzg2l_du_atomic_commit_tail(struct drm_atomic_state
> > *old_state)
> > > +{
> > > + struct drm_device *dev = old_state->dev;
> > > +
> > > + /* Apply the atomic update. */
> > > + drm_atomic_helper_commit_modeset_disables(dev, old_state);
> > > + drm_atomic_helper_commit_planes(dev, old_state,
> > > + DRM_PLANE_COMMIT_ACTIVE_ONLY);
> > > + drm_atomic_helper_commit_modeset_enables(dev, old_state);
> > > +
> > > + drm_atomic_helper_commit_hw_done(old_state);
> > > + drm_atomic_helper_wait_for_flip_done(dev, old_state);
> > > +
> > > + drm_atomic_helper_cleanup_planes(dev, old_state);
> > > +}
> > > +
> > > +/* -------------------------------------------------------------------
> -
> > ---------
> > > + * Initialization
> > > + */
> > > +
> > > +static const struct drm_mode_config_helper_funcs
> > rzg2l_du_mode_config_helper = {
> > > + .atomic_commit_tail = rzg2l_du_atomic_commit_tail,
> > > +};
> > > +
> > > +static const struct drm_mode_config_funcs rzg2l_du_mode_config_funcs =
> > {
> > > + .fb_create = rzg2l_du_fb_create,
> > > + .atomic_check = drm_atomic_helper_check,
> > > + .atomic_commit = drm_atomic_helper_commit,
> > > +};
> > > +
> > > +static int rzg2l_du_encoders_init_one(struct rzg2l_du_device *rcdu,
> > > + enum rzg2l_du_output output,
> > > + struct of_endpoint *ep)
> > > +{
> > > + struct device_node *entity;
> > > + int ret;
> > > +
> > > + /* Locate the connected entity and initialize the encoder. */
> > > + entity = of_graph_get_remote_port_parent(ep->local_node);
> > > + if (!entity) {
> > > + dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
> > > + ep->local_node);
> > > + return -ENODEV;
> > > + }
> > > +
> > > + if (!of_device_is_available(entity)) {
> > > + dev_dbg(rcdu->dev,
> > > + "connected entity %pOF is disabled, skipping\n",
> > > + entity);
> > > + of_node_put(entity);
> > > + return -ENODEV;
> > > + }
> > > +
> > > + ret = rzg2l_du_encoder_init(rcdu, output, entity);
> > > + if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)
> > > + dev_warn(rcdu->dev,
> > > + "failed to initialize encoder %pOF on output %s (%d),
> > skipping\n",
> > > + entity, rzg2l_du_output_name(output), ret);
> > > +
> > > + of_node_put(entity);
> > > +
> > > + return ret;
> > > +}
> > > +
> > > +static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu)
> > > +{
> > > + struct device_node *np = rcdu->dev->of_node;
> > > + struct device_node *ep_node;
> > > + unsigned int num_encoders = 0;
> > > +
> > > + /*
> > > + * Iterate over the endpoints and create one encoder for each output
> > > + * pipeline.
> > > + */
> > > + for_each_endpoint_of_node(np, ep_node) {
> > > + enum rzg2l_du_output output;
> > > + struct of_endpoint ep;
> > > + unsigned int i;
> > > + int ret;
> > > +
> > > + ret = of_graph_parse_endpoint(ep_node, &ep);
> > > + if (ret < 0) {
> > > + of_node_put(ep_node);
> > > + return ret;
> > > + }
> > > +
> > > + /* Find the output route corresponding to the port number. */
> > > + for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) {
> > > + if (rcdu->info->routes[i].possible_crtcs &&
> >
> > This seems to always be true
>
> OK will remove it.
>
> >
> > > + rcdu->info->routes[i].port == ep.port) {
> > > + output = i;
> > > + break;
> > > + }
> > > + }
> > > +
> > > + if (i == RZG2L_DU_OUTPUT_MAX) {
> > > + dev_warn(rcdu->dev,
> > > + "port %u references unexisting output,
> > skipping\n",
> > > + ep.port);
> > > + continue;
> > > + }
> > > +
> > > + /* Process the output pipeline. */
> > > + ret = rzg2l_du_encoders_init_one(rcdu, output, &ep);
> > > + if (ret < 0) {
> > > + if (ret == -EPROBE_DEFER) {
> > > + of_node_put(ep_node);
> > > + return ret;
> > > + }
> > > +
> > > + continue;
> > > + }
> > > +
> > > + num_encoders++;
> > > + }
> > > +
> > > + return num_encoders;
> > > +}
> > > +
> > > +static int rzg2l_du_properties_init(struct rzg2l_du_device *rcdu)
> > > +{
> > > + /*
> > > + * The color key is expressed as an RGB888 triplet stored in a 32-
> > bit
> > > + * integer in XRGB8888 format. Bit 24 is used as a flag to disable
> > (0)
> > > + * or enable source color keying (1).
> > > + */
> > > + rcdu->props.colorkey =
> > > + drm_property_create_range(&rcdu->ddev, 0, "colorkey",
> > > + 0, 0x01ffffff);
> > > + if (!rcdu->props.colorkey)
> > > + return -ENOMEM;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int rzg2l_du_vsps_init(struct rzg2l_du_device *rcdu)
> > > +{
> > > + const struct device_node *np = rcdu->dev->of_node;
> > > + const char *vsps_prop_name = "renesas,vsps";
> > > + struct of_phandle_args args;
> > > + struct {
> > > + struct device_node *np;
> > > + unsigned int crtcs_mask;
> > > + } vsps[RZG2L_DU_MAX_VSPS] = { { NULL, }, };
> > > + unsigned int vsps_count = 0;
> > > + unsigned int cells;
> > > + unsigned int i;
> > > + int ret;
> > > +
> > > + /*
> > > + * First parse the DT vsps property to populate the list of VSPs.
> > Each
> > > + * entry contains a pointer to the VSP DT node and a bitmask of the
> > > + * connected DU CRTCs.
> > > + */
> > > + ret = of_property_count_u32_elems(np, vsps_prop_name);
> > > + if (ret < 0) {
> > > + /* Backward compatibility with old DTBs. */
> > > + vsps_prop_name = "vsps";
> > > + ret = of_property_count_u32_elems(np, vsps_prop_name);
> > > + }
> > > + cells = ret / rcdu->num_crtcs - 1;
> > > + if (cells > 1)
> > > + return -EINVAL;
> > > +
> > > + for (i = 0; i < rcdu->num_crtcs; ++i) {
> > > + unsigned int j;
> > > +
> > > + ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,
> > > + cells, i, &args);
> > > + if (ret < 0)
> > > + goto error;
> > > +
> > > + /*
> > > + * Add the VSP to the list or update the corresponding
> > existing
> > > + * entry if the VSP has already been added.
> > > + */
> > > + for (j = 0; j < vsps_count; ++j) {
> > > + if (vsps[j].np == args.np)
> > > + break;
> > > + }
> > > +
> > > + if (j < vsps_count)
> > > + of_node_put(args.np);
> > > + else
> > > + vsps[vsps_count++].np = args.np;
> > > +
> > > + vsps[j].crtcs_mask |= BIT(i);
> > > +
> > > + /*
> > > + * Store the VSP pointer and pipe index in the CRTC. If the
> > > + * second cell of the 'renesas,vsps' specifier isn't present,
> > > + * default to 0 to remain compatible with older DT bindings.
> > > + */
> > > + rcdu->crtcs[i].vsp = &rcdu->vsps[j];
> > > + rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
> >
> > Are there mulitple LIFs on RZ/G2L ?
>
> No, single LIF.
>
> >
> > > + }
> > > +
> > > + /*
> > > + * Then initialize all the VSPs from the node pointers and CRTCs
> > bitmask
> > > + * computed previously.
> > > + */
> > > + for (i = 0; i < vsps_count; ++i) {
> > > + struct rzg2l_du_vsp *vsp = &rcdu->vsps[i];
> > > +
> > > + vsp->index = i;
> > > + vsp->dev = rcdu;
> > > +
> > > + ret = rzg2l_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
> > > + if (ret < 0)
> > > + goto error;
> > > + }
> > > +
> > > + return 0;
> > > +
> > > +error:
> > > + for (i = 0; i < ARRAY_SIZE(vsps); ++i)
> > > + of_node_put(vsps[i].np);
> > > +
> > > + return ret;
> > > +}
> > > +
> > > +int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu)
> > > +{
> > > + struct drm_device *dev = &rcdu->ddev;
> > > + struct drm_encoder *encoder;
> > > + unsigned int num_encoders;
> > > + int ret;
> > > +
> > > + ret = drmm_mode_config_init(dev);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + dev->mode_config.min_width = 0;
> > > + dev->mode_config.min_height = 0;
> > > + dev->mode_config.normalize_zpos = true;
> > > + dev->mode_config.funcs = &rzg2l_du_mode_config_funcs;
> > > + dev->mode_config.helper_private = &rzg2l_du_mode_config_helper;
> > > +
> > > + /*
> > > + * The RZ DU uses the VSP1 for memory access, and is limited
> > > + * to frame sizes of 1920x1080.
> > > + */
> > > + dev->mode_config.max_width = 1920;
> > > + dev->mode_config.max_height = 1080;
> > > +
> > > + rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
> >
> > Isn't this fixed ?
> > Do you expect other SoCs of the same product line to have multiple
> > CRTCs ?
>
> Currently, I do not know. But prefer to keep it generic for now.
>
> >
> > Thanks and sorry for the many questions!
>
> OK.
>
> Cheers,
> Biju
