On 29/08/2023 19:16, Alex Bee wrote:
> From: Finley Xiao <finley.xiao@xxxxxxxxxxxxxx>
>
> According to the TRM there are no specific cpll_peri, gpll_div2_peri or
> gpll_div3_peri gates, but a single clk_peri_src gate and the peri mux
> directly connects to the plls respectivly the pll divider clocks.
> Fix this by creating a single gated composite.
>
> Also rename all occurrences of "aclk_peri_src*" to clk_peri_src, since it
> is the parent for both peri aclks and hclks and that also matches the
> naming in the TRM.
>
> Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
> Signed-off-by: Finley Xiao <finley.xiao@xxxxxxxxxxxxxx>
> [renamed aclk_peri_src -> clk_peri_src and added commit message]
> Signed-off-by: Alex Bee <knaerzche@xxxxxxxxx>
Please send fixes as separate patchset. Don't mix it with other work and
definitely it should not be in the middle of the patchset.
Best regards,
Krzysztof
