This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel. Reviewed-by: Rob Herring <robh@xxxxxxxxxx> Signed-off-by: Liu Ying <victor.liu@xxxxxxx> --- v10->v14: * No change. v9->v10: * Add Rob's R-b tag. v8->v9: * Reference 'interrupts-extended' schema instead of 'interrupts' to require an additional interrupt(r_rtram_stall) because the reference manual does mention it, though the driver doesn't get/use it for now. Reference 'interrupt-names' schema to define the two interrupt names - 'dpr_wrap' and 'r_rtram_stall'. * Drop Rob's R-b tag, as review is needed. v4->v8: * No change. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Use new dt binding way to add clocks in the example. .../display/imx/fsl,imx8qxp-dprc.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml new file mode 100644 index 000000000000..bd94254c1288 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel + +maintainers: + - Liu Ying <victor.liu@xxxxxxx> + +description: | + The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which + fetches display data before the display pipeline needs the data to drive + pixels in the active display region. This data is transformed, or resolved, + from a variety of tiled buffer formats into linear format, if needed. + The DPR works with a double bank memory structure. This memory structure is + implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to + as A and B. Each bank is either 4 or 8 lines high depending on the source + frame buffer format. + +properties: + compatible: + enum: + - fsl,imx8qxp-dpr-channel + - fsl,imx8qm-dpr-channel + + reg: + maxItems: 1 + + interrupts-extended: + items: + - description: DPR wrap interrupt + - description: | + 'r_rtram_stall' interrupt which indicates relevant i.MX8qm/qxp + Prefetch Resolve Gasket(PRG) or PRGs are forcing an underflow + condition in the RTRAM. + + interrupt-names: + items: + - const: dpr_wrap + - const: r_rtram_stall + + clocks: + items: + - description: apb clock + - description: b clock + - description: rtram clock + + clock-names: + items: + - const: apb + - const: b + - const: rtram + + fsl,sc-resource: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The SCU resource ID associated with this DPRC instance. + + fsl,prgs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle which points to PRG or PRGs associated with + this DPRC instance. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts-extended + - interrupt-names + - clocks + - clock-names + - fsl,sc-resource + - fsl,prgs + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + dpr-channel@56100000 { + compatible = "fsl,imx8qxp-dpr-channel"; + reg = <0x56100000 0x10000>; + interrupts-extended = <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <&dc0_irqsteer 324>; + interrupt-names = "dpr_wrap", "r_rtram_stall"; + clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>, + <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>, + <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>; + clock-names = "apb", "b", "rtram"; + fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO0>; + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; + power-domains = <&pd IMX_SC_R_DC_0>; + }; -- 2.37.1
