This one doesn't apply cleanly.
Alex
On Mon, Jul 24, 2023 at 4:54 AM <sunran001@xxxxxxxxxx> wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: trailing whitespace
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun <sunran001@xxxxxxxxxx>
> ---
> .../amd/pm/swsmu/inc/smu_v11_0_7_pptable.h | 41 +++++++++----------
> 1 file changed, 19 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> index 1cb399dbc7cc..64d60d48846a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> @@ -42,23 +42,23 @@
> #define SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01
> // Power Saving Clock Table Version 1.00
>
> enum SMU_11_0_7_ODFEATURE_CAP {
> - SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0,
> - SMU_11_0_7_ODCAP_GFXCLK_CURVE,
> - SMU_11_0_7_ODCAP_UCLK_LIMITS,
> - SMU_11_0_7_ODCAP_POWER_LIMIT,
> - SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,
> - SMU_11_0_7_ODCAP_FAN_SPEED_MIN,
> - SMU_11_0_7_ODCAP_TEMPERATURE_FAN,
> - SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,
> - SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,
> - SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL,
> - SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,
> - SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,
> - SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,
> + SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0,
> + SMU_11_0_7_ODCAP_GFXCLK_CURVE,
> + SMU_11_0_7_ODCAP_UCLK_LIMITS,
> + SMU_11_0_7_ODCAP_POWER_LIMIT,
> + SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,
> + SMU_11_0_7_ODCAP_FAN_SPEED_MIN,
> + SMU_11_0_7_ODCAP_TEMPERATURE_FAN,
> + SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,
> + SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,
> + SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL,
> + SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,
> + SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,
> + SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,
> SMU_11_0_7_ODCAP_FAN_CURVE,
> SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,
> - SMU_11_0_7_ODCAP_POWER_MODE,
> - SMU_11_0_7_ODCAP_COUNT,
> + SMU_11_0_7_ODCAP_POWER_MODE,
> + SMU_11_0_7_ODCAP_COUNT,
> };
>
> enum SMU_11_0_7_ODFEATURE_ID {
> @@ -130,8 +130,7 @@ enum SMU_11_0_7_PWRMODE_SETTING {
> };
> #define SMU_11_0_7_MAX_PMSETTING 32 //Maximum Number of
> PowerMode Settings
>
> -struct smu_11_0_7_overdrive_table
> -{
> +struct smu_11_0_7_overdrive_table {
> uint8_t revision;
> //Revision = SMU_11_0_7_PP_OVERDRIVE_VERSION
> uint8_t reserve[3]; //Zero
> filled field reserved for future use
> uint32_t feature_count; //Total
> number of supported features
> @@ -160,8 +159,7 @@ enum SMU_11_0_7_PPCLOCK_ID {
> };
> #define SMU_11_0_7_MAX_PPCLOCK 16 //Maximum Number of PP
> Clocks
>
> -struct smu_11_0_7_power_saving_clock_table
> -{
> +struct smu_11_0_7_power_saving_clock_table {
> uint8_t revision;
> //Revision = SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION
> uint8_t reserve[3]; //Zero
> filled field reserved for future use
> uint32_t count;
> //power_saving_clock_count = SMU_11_0_7_PPCLOCK_COUNT
> @@ -169,8 +167,7 @@ struct smu_11_0_7_power_saving_clock_table
> uint32_t min[SMU_11_0_7_MAX_PPCLOCK];
> //PowerSavingClock Mode Clock Minimum array In MHz
> };
>
> -struct smu_11_0_7_powerplay_table
> -{
> +struct smu_11_0_7_powerplay_table {
> struct atom_common_table_header header; //For
> sienna_cichlid, header.format_revision = 15, header.content_revision = 0
> uint8_t table_revision; //For
> sienna_cichlid, table_revision = 2
> uint16_t table_size; //Driver portion
> table size. The offset to smc_pptable including header size
> @@ -178,7 +175,7 @@ struct smu_11_0_7_powerplay_table
> uint32_t golden_revision; //PPGen use only:
> PP Table Revision on the Golden Data Base
> uint16_t format_id; //PPGen use only:
> PPTable for different ASICs. For sienna_cichlid this should be 0x80
> uint32_t platform_caps;
> //POWERPLAYABLE::ulPlatformCaps
> -
> +
> uint8_t thermal_controller_type; //one of
> SMU_11_0_7_PP_THERMALCONTROLLER
>
> uint16_t small_power_limit1;
