Ops... sorry... I am realizing that I sent again V6... please
ignore this series!
Andi
On Thu, Jul 20, 2023 at 06:44:45PM +0200, Andi Shyti wrote:
> Hi,
>
> as there are new hardware directives, we need a little adaptation
> for the AUX invalidation sequence.
>
> In this version we support all the engines affected by this
> change.
>
> The stable backport has some challenges because the original
> patch that this series fixes has had more changes in between.
>
> This patch is slowly exploding with code refactorings and
> features added and fixed.
>
> Thanks a lot Nirmoy, Andrzej and Matt for your review and for the
> fruitful discussions!
>
> Thanks,
> Andi
>
> Changelog:
> =========
> v5 -> v6
> - Fixed ccs flush in the engines VE and BCS. They are sent as a
> separate command instead of added in the pipe control.
> - Separated the CCS flusing in the pipe control patch with the
> quiescing of the memory. They were meant to be on separate
> patch already in the previous verision, but apparently I
> squashed them by mistake.
>
> v4 -> v5
> - The AUX CCS is added as a device property instead of checking
> against FLAT CCS. This adds the new HAS_AUX_CCS check
> (Patch 2, new).
> - little and trivial refactoring here and there.
> - extended the flags{0,1}/bit_group_{0,1} renaming to other
> functions.
> - Created an intel_emit_pipe_control_cs() wrapper for submitting
> the pipe control.
> - Quiesce memory for all the engines, not just RCS (Patch 6,
> new).
> - The PIPE_CONTROL_CCS_FLUSH is added to all the engines.
> - Remove redundant EMIT_FLUSH_CCS mode flag.
> - Remove unnecessary NOOPs from the command streamer for
> invalidating the CCS table.
> - Use INVALID_MMIO_REG and gen12_get_aux_inv_reg() instad of
> __MMIO(0) and reg.reg.
> - Remove useless wrapper and just use gen12_get_aux_inv_reg().
>
> v3 -> v4
> - A trivial patch 3 is added to rename the flags with
> bit_group_{0,1} to align with the datasheet naming.
> - Patch 4 fixes a confusion I made where the CCS flag was
> applied to the wrong bit group.
>
> v2 -> v3
> - added r-b from Nirmoy in patch 1 and 4.
> - added patch 3 which enables the ccs_flush in the control pipe
> for mtl+ compute and render engines.
> - added redundant checks in patch 2 for enabling the EMIT_FLUSH
> flag.
>
> v1 -> v2
> - add a clean up preliminary patch for the existing registers
> - add support for more engines
> - add the Fixes tag
>
> Andi Shyti (7):
> drm/i915/gt: Cleanup aux invalidation registers
> drm/i915: Add the has_aux_ccs device property
> drm/i915/gt: Rename flags with bit_group_X according to the datasheet
> drm/i915/gt: Refactor intel_emit_pipe_control_cs() in a single
> function
> drm/i915/gt: Ensure memory quiesced before invalidation for all
> engines
> drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control
> drm/i915/gt: Support aux invalidation on all engines
>
> Jonathan Cavitt (2):
> drm/i915/gt: Ensure memory quiesced before invalidation
> drm/i915/gt: Poll aux invalidation register bit on invalidation
>
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 222 +++++++++++++------
> drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 21 +-
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 16 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +-
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 5 +-
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 8 files changed, 186 insertions(+), 99 deletions(-)
>
> --
> 2.40.1
