On Thu, Jul 6, 2023 at 7:29 PM Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> wrote: > > On 07/07/2023 00:10, Rob Clark wrote: > > From: Rob Clark <robdclark@xxxxxxxxxxxx> > > > > It is better to explicitly list it. With the move to opaque chip-id's > > for future devices, we should avoid trying to infer things like > > generation from the numerical value. > > Would it be better to push this to DT? I mean, we already have a > 'dma-cache-coherent' property for it. I suppose that would also handle the case where some a6xy are coherent but others aren't.. OTOH it isn't the case that dma operations are coherent, just that they can be. It depends on smmu pte bits. Maybe that bit of pedanticism doesn't matter since we mostly bypass the dma api, but we still do need to (ab)use dma_map_sgtable/dma_unmap_sgtable for cache ops BR, -R > > > > Signed-off-by: Rob Clark <robdclark@xxxxxxxxxxxx> > > --- > > drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++------- > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + > > 2 files changed, 17 insertions(+), 7 deletions(-) > > > > -- > With best wishes > Dmitry >
