From: Rob Clark <robdclark@xxxxxxxxxxxx> Downstream seems to be moving to using the chip_id as simply an opaque identifier, and if we want to avoid headaches with userspace mesa supporting both kgsl and upstream, we should move away from the assumption that certain bits in the chip_id have a specific meaning. Patches 6 and 7 were something that I came up with before Konrad suggesting moving fuse/speedbin mapping to a separate per-SoC table. Which I guess would also work. But I guess if we did that, we'd want to move things like whether cached-coherent is supported to that table as well. I'm not a huge fan of pretending that whether or not you have cached-coherent is anything to do with GMU itself, rather than just a happy coincidence. Rob Clark (12): drm/msm/adreno: Remove GPU name drm/msm/adreno: Remove redundant gmem size param drm/msm/adreno: Remove redundant revn param drm/msm/adreno: Use quirk identify hw_apriv drm/msm/adreno: Use quirk to identify cached-coherent support drm/msm/adreno: Allow SoC specific gpu device table entries drm/msm/adreno: Move speedbin mapping to device table drm/msm/adreno: Bring the a630 family together drm/msm/adreno: Add adreno family drm/msm/adreno: Add helper for formating chip-id dt-bindings: drm/msm/gpu: Extend bindings for chip-id drm/msm/adreno: Switch to chip-id for identifying GPU .../devicetree/bindings/display/msm/gpu.yaml | 6 + drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 13 +- drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 187 ++---------- drivers/gpu/drm/msm/adreno/adreno_device.c | 282 ++++++++++++------ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 52 ++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 150 +++++++--- 10 files changed, 362 insertions(+), 349 deletions(-) -- 2.41.0
