Currently we assume 2 Pixels Per Clock (PPC) while computing plane cdclk and min_cdlck. In cases where DSC single engine is used the throughput is 1 PPC. So account for the above case, while computing cdclk. v2: Use helper to get the adjusted pixel rate. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++- drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 4207863b7b2a..990dc16511f9 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -37,6 +37,7 @@ #include "intel_pci_config.h" #include "intel_pcode.h" #include "intel_psr.h" +#include "intel_vdsc.h" #include "vlv_sideband.h" /** @@ -2507,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) int pixel_rate = crtc_state->pixel_rate; if (DISPLAY_VER(dev_priv) >= 10) - return DIV_ROUND_UP(pixel_rate, 2); + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate); else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return pixel_rate; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index bd9116d2cd76..11227491834e 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -974,3 +974,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) out: intel_display_power_put(dev_priv, power_domain, wakeref); } + +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate) +{ + /* + * If single VDSC engine is used, it uses one pixel per clock + * otherwise we use two pixels per clock. + */ + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) + return pixel_rate; + + return DIV_ROUND_UP(pixel_rate, 2); +} diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 8763f00fa7e2..9f21a6c565c6 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -27,4 +27,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate); + #endif /* __INTEL_VDSC_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 6b01a0b68b97..9eeb25ec4be9 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -17,6 +17,7 @@ #include "intel_fb.h" #include "intel_fbc.h" #include "intel_psr.h" +#include "intel_vdsc.h" #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_watermark.h" @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, { unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); - /* two pixels per clock */ - return DIV_ROUND_UP(pixel_rate, 2); + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate); } static void -- 2.40.1