On 2023-06-24 03:45:02, Konrad Dybcio wrote:
> On 24.06.2023 02:41, Marijn Suijten wrote:
> > The "gcc_disp_gpll0_div_clk_src" clock is consumed by the driver, will
> > be passed from DT, and should be required by the bindings.
> >
> > Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings")
> > Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
> > ---
> Ideally, you'd stick it at the bottom of the list, as the items: order
> is part of the ABI
This isn't an ABI break, as this driver nor its bindings require/declare
a fixed order: they declare a relation between clocks and clock-names.
This orders the GCC clock just like other dispccs. And the previous
patch dropped the unused cfg_ahb_clk from the bindings, so all bets are
off anyway.
- Marijn
>
> Konrad
> > Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
> > index 2acf487d8a2f..11ec154503a3 100644
> > --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
> > +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
> > @@ -23,6 +23,7 @@ properties:
> > clocks:
> > items:
> > - description: Board XO source
> > + - description: GPLL0 div source from GCC
> > - description: Byte clock from DSI PHY0
> > - description: Pixel clock from DSI PHY0
> > - description: Pixel clock from DSI PHY1
> > @@ -32,6 +33,7 @@ properties:
> > clock-names:
> > items:
> > - const: bi_tcxo
> > + - const: gcc_disp_gpll0_div_clk_src
> > - const: dsi0_phy_pll_out_byteclk
> > - const: dsi0_phy_pll_out_dsiclk
> > - const: dsi1_phy_pll_out_dsiclk
> > @@ -65,12 +67,14 @@ examples:
> > compatible = "qcom,sm6125-dispcc";
> > reg = <0x5f00000 0x20000>;
> > clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
> > <&dsi0_phy 0>,
> > <&dsi0_phy 1>,
> > <&dsi1_phy 1>,
> > <&dp_phy 0>,
> > <&dp_phy 1>;
> > clock-names = "bi_tcxo",
> > + "gcc_disp_gpll0_div_clk_src",
> > "dsi0_phy_pll_out_byteclk",
> > "dsi0_phy_pll_out_dsiclk",
> > "dsi1_phy_pll_out_dsiclk",
> >
