On 23/06/2023 03:01, Abhinav Kumar wrote:
On 6/14/2023 2:56 AM, Marijn Suijten wrote:
On 2023-06-13 18:57:13, Jessica Zhang wrote:
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as recommend by the hardware programming guide.
Only enable this for command mode as we are currently unable to validate
it for video mode.
Signed-off-by: Jessica Zhang <quic_jesszhan@xxxxxxxxxxx>
---
Note: The dsi.xml.h changes were generated using the headergen2
script in
envytools [1], but the changes to the copyright and rules-ng-ng
source file
paths were dropped.
[1] https://github.com/freedreno/envytools/
More interesting would be a link to the Mesa MR upstreaming this
bitfield to dsi.xml [2] (which I have not found on my own yet).
[2]:
https://gitlab.freedesktop.org/mesa/mesa/-/blame/main/src/freedreno/registers/dsi/dsi.xml
Thats because we havent submitted a MR yet for this on mesa.
Generally, our team does not have legal permissions yet for mesa MRs
other than mesa drm because we got permissions for the modetest.
Rob/Dmitry, can one of you pls help with the corresponding mesa MR for
this?
The xml file change was autogenerated so this patch can go in.
Ack, I'll handle it.
--
With best wishes
Dmitry
