>
> Module level clock gating and the pulse eater might interfere with
> the GPU reset, as they both have the potential to stop the clock
> and thus reset propagation to parts of the GPU.
>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Reviewed-by: Christian Gmeiner <cgmeiner@xxxxxxxxxx>
> ---
> I'm not aware of any cases where this would have been an issue, but
> it is what the downstream driver does and fundametally seems like
> the right thing to do.
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index de8c9894967c..41aab1aa330b 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -505,8 +505,19 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
> timeout = jiffies + msecs_to_jiffies(1000);
>
> while (time_is_after_jiffies(timeout)) {
> - /* enable clock */
> unsigned int fscale = 1 << (6 - gpu->freq_scale);
> + u32 pulse_eater = 0x01590880;
> +
> + /* disable clock gating */
> + gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0);
> +
> + /* disable pulse eater */
> + pulse_eater |= BIT(17);
> + gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
> + pulse_eater |= BIT(0);
> + gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
> +
> + /* enable clock */
> control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
> etnaviv_gpu_load_clock(gpu, control);
>
> --
> 2.39.2
>
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
