On 2023/6/7 22:03, Doug Anderson wrote:
Hi, On Tue, Jun 6, 2023 at 6:25 PM Su Hui <suhui@xxxxxxxxxxxx> wrote:Smatch error:buffer overflow 'ti_sn_bridge_refclk_lut' 5 <= 5. Fixes: cea86c5bb442 ("drm/bridge: ti-sn65dsi86: Implement the pwm_chip") Signed-off-by: Su Hui <suhui@xxxxxxxxxxxx> --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 7a748785c545..bb88406495e9 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -305,7 +305,7 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata) * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, * regardless of its actual sourcing. */ - pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; + pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i < refclk_lut_size ? i : 1];This looks more correct, but it really needs a comment since it's totally not obviously what you're doing here. IMO the best solution here is to update "i" right after the for loop and have a comment about the datasheet saying that "1" is the default rate so we'll fall back to that if we couldn't find a match. Moving it to right after the for loop will change the value written into the registers, but that's fine and makes it clearer what's happening.
Got it. Add some comment and move the code up. I will send patch v3 soon. Thanks for your suggestion again :) . Su Hui
-Doug
