Hi Neil, On Tue, May 30, 2023 at 5:57 PM Neil Armstrong <neil.armstrong@xxxxxxxxxx> wrote: [...] > >> The mipi_dsi_pxclk_div is set as RO in order to use the same GP0 > >> for mipi_dsi_pxclk and vclk2_input. > > > > I don't think notifiers is the appropriate approach here. > > Whenever there is clock change the motifiers would trigger an off/on of > > the clock, regardless of the clock usage or state. > > If you have several consummers on this vclk2, this would > > cause glitches and maybe this is not desirable. > > > > I think it would be better to handle the enable and reset with a > > specific gate driver, in prepare() or enable(), and the give the clock > > CLK_SET_RATE_GATE flag. > > > > This would require the clock to be properly turn off before changing the > > rate. > > Sure, will see how to switch to that, seem Martin did than on Meson8. You can start here: [0] It may not be the nicest logic but so far it works (for me). Please note that I don't mix between CCF and direct register IO clock handling: For the old SoCs I'm relying only on CCF to manage the clocks. Best regards, Martin [0] https://github.com/xdarklight/linux/blob/meson-mx-integration-6.3-20230410/drivers/gpu/drm/meson/meson_vclk.c#L1177-L1179
