Re: [PATCH v4 4/5] drm/msm/dpu: Set DATA_COMPRESS for command mode

[Jessica Zhang <quic_jesszhan@xxxxxxxxxxx>]

On 5/22/2023 1:54 PM, Marijn Suijten wrote:
> How about: Enable INTF DATA_COMPRESS bit (on cmdmode) for DCE/DSC 1.2?

Hi Marijn,

Acked.

> Drop parenthesis at your convenience.
>
> On 2023-05-22 13:30:23, Jessica Zhang wrote:
> > Add a DPU INTF op to set DATA_COMPRESS register if the
> > DPU_INTF_DATA_COMPRESS feature is enabled. This bit needs to be set in
> > order for DSC v1.2 to work.
>
> "in order for .. to work" sounds like bugfixing... How about just:
> "set the DCE_DATA_COMPRESS bit to enable the DCE/DSC 1.2 datapath",
> which I think is what it is doing?  Everyone seems to favour the
> "datapath" word anyway :)

Sounds good.

Thanks,

Jessica Zhang

> > Note: For now, this op is called for command mode encoders only. Changes to
> > set DATA_COMPRESS for video mode encoders will be posted along with DSC
> > v1.2 support for DP.
> >
> > Signed-off-by: Jessica Zhang <quic_jesszhan@xxxxxxxxxxx>
> > ---
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c |  3 +++
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c          | 13 +++++++++++++
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h          |  2 ++
> >   3 files changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > index d8ed85a238af..1a4c20f02312 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > @@ -68,6 +68,9 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> >   				phys_enc->hw_intf,
> >   				true,
> >   				phys_enc->hw_pp->idx);
> > +
> > +	if (phys_enc->hw_intf->ops.enable_compression)
> > +		phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
> >   }
> >   
> >   static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > index 6485500eedb8..a462c6780e6e 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > @@ -91,6 +91,7 @@
> >   
> >   #define INTF_CFG2_DATABUS_WIDEN	BIT(0)
> >   #define INTF_CFG2_DATA_HCTL_EN	BIT(4)
> > +#define INTF_CFG2_DCE_DATA_COMPRESS     BIT(12)
> >   
> >   static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
> >   		const struct intf_timing_params *p,
> > @@ -522,6 +523,15 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,
> >   
> >   }
> >   
> > +static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
> > +{
> > +	u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2);
> > +
> > +	intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
> > +
> > +	DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
> > +}
> > +
> >   static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
> >   		unsigned long cap)
> >   {
> > @@ -542,6 +552,9 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
> >   		ops->vsync_sel = dpu_hw_intf_vsync_sel;
> >   		ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
> >   	}
> > +
> > +	if (cap & BIT(DPU_INTF_DATA_COMPRESS))
> > +		ops->enable_compression = dpu_hw_intf_enable_compression;
> >   }
> >   
> >   struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> > index 73b0885918f8..72fe907729f1 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> > @@ -70,6 +70,7 @@ struct intf_status {
> >    * @get_autorefresh:            Retrieve autorefresh config from hardware
> >    *                              Return: 0 on success, -ETIMEDOUT on timeout
> >    * @vsync_sel:                  Select vsync signal for tear-effect configuration
> > + * @enable_compression:         Enable data compression
> >    */
> >   struct dpu_hw_intf_ops {
> >   	void (*setup_timing_gen)(struct dpu_hw_intf *intf,
> > @@ -107,6 +108,7 @@ struct dpu_hw_intf_ops {
> >   	 * Disable autorefresh if enabled
> >   	 */
> >   	void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay);
>
> Newline here.
>
>
> For the contents of the patch though:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
>
> > +	void (*enable_compression)(struct dpu_hw_intf *intf);
> >   };
> >   
> >   struct dpu_hw_intf {
> >
> > --
> > 2.40.1