We have the necessary information, so explain which bit does what. Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 9fb214f150dd..deed42675fe2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -771,9 +771,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) } /* - * Enable access protection to privileged registers, fault on an access - * protect violation and select the last span to protect from the start - * address all the way to the end of the register address space + * BIT(0) - Enable access protection to privileged registers + * BIT(1) - Enable fault on an access protect violation + * BIT(3) - Select the last span to protect from the start + * address all the way to the end of the register address space */ gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)); -- 2.40.1
